SLVSIF3B February   2025  – August 2026 TPS561300

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Fixed-Frequency PWM Control
      2. 6.3.2  Pulse Frequency Mode
      3. 6.3.3  Error Amplifier
      4. 6.3.4  Slope Compensation and Output Current
      5. 6.3.5  Enable and Adjusting Undervoltage Lockout
      6. 6.3.6  Safe Start-Up into Prebiased Outputs
      7. 6.3.7  Voltage Reference
      8. 6.3.8  Adjusting Output Voltage
      9. 6.3.9  Internal Soft Start
      10. 6.3.10 Bootstrap Voltage (BOOT)
      11. 6.3.11 Overcurrent Protection
        1. 6.3.11.1 High-Side MOSFET Overcurrent Protection
        2. 6.3.11.2 Low-Side MOSFET Overcurrent Protection
      12. 6.3.12 Spread Spectrum
      13. 6.3.13 Output Overvoltage Protection (OVP)
      14. 6.3.14 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Eco-mode Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 TPS561300 5V to 30V Input, 5V Output Converter
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Input Capacitor Selection
        2. 7.2.3.2 Bootstrap Capacitor Selection
        3. 7.2.3.3 Output Voltage Setpoint
        4. 7.2.3.4 Undervoltage Lockout Setpoint
        5. 7.2.3.5 Inductor Selection
        6. 7.2.3.6 Output Capacitor Selection
        7. 7.2.3.7 Feed-Forward Capacitor
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.4 Thermal Information

THERMAL METRIC (1)TPS561300UNIT
DDC (SOT-23-THN, 6)
JEDEC(2)EVM(3)
RθJAJunction-to-ambient thermal resistance118.6N/A°C/W
RθJC(top)Junction-to-case (top) thermal resistance63.6N/A°C/W
RθJBJunction-to-board thermal resistance34.4N/A°C/W
ψJTJunction-to-top characterization parameter18.5N/A°C/W
ψJBJunction-to-board characterization parameter33.7N/A°C/W
RθJA_EVMJunction-to-ambient thermal resistance on official EVM boardN/A57.2°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.
(2) The value of RθJA given in this table is only valid for comparison with other packages and can not be used for design purposes. These values were simulated on a standard JEDEC board. These values do not represent the performance obtained in an actual application.
(3) The effective RθJA is tested on the official EVM board.