SLVSIQ9 February   2026 MSPM0G1218

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      10
    3. 6.3 Signal Descriptions
      1.      12
      2.      13
      3.      14
      4.      15
      5.      16
      6.      17
      7.      18
      8.      19
      9.      20
      10.      21
      11.      22
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
      2. 7.6.2 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1  Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF1
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 VREF2
      1. 7.15.1 Voltage Characteristics
      2. 7.15.2 Electrical Characteristics
    16. 7.16 Comparator (COMP)
      1. 7.16.1 Comparator Electrical Characteristics
    17. 7.17 I2C
      1. 7.17.1 I2C Characteristics
      2. 7.17.2 I2C Filter
      3. 7.17.3 I2C Timing Diagram
    18. 7.18 SPI
      1. 7.18.1 SPI
      2. 7.18.2 SPI Timing Diagram
    19. 7.19 UART
    20. 7.20 TIMx
    21. 7.21 TRNG
      1. 7.21.1 TRNG Electrical Characteristics
    22. 7.22 Emulation and Debug
      1. 7.22.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  Functional Block Diagram
    2. 8.2  CPU
    3. 8.3  Operating Modes
      1. 8.3.1 Functionality by Operating Mode (MSPM0Gx218, MSPM0Gx207, MSPM0G122x)
    4. 8.4  Power Management Unit (PMU)
    5. 8.5  Clock Module (CKM)
    6. 8.6  DMA
    7. 8.7  Events
    8. 8.8  Memory
      1. 8.8.1 Memory Organization
      2. 8.8.2 Peripherals Summary
      3. 8.8.3 Peripheral Interrupt Vector
    9. 8.9  Flash Memory
    10. 8.10 SRAM
    11. 8.11 GPIO
    12. 8.12 IOMUX
    13. 8.13 ADC
    14. 8.14 Temperature Sensor
    15. 8.15 VREF
    16. 8.16 COMP
    17. 8.17 Security
    18. 8.18 AESADV
    19. 8.19 Keystore
    20. 8.20 CRC-P
    21. 8.21 MATHACL
    22. 8.22 UNICOMM (UART/SPI/I2C)
      1. 8.22.1 UART (UNICOMM)
      2. 8.22.2 I2C (UNICOMM)
      3. 8.22.3 SPI (UNICOMM)
    23. 8.23 UART
    24. 8.24 I2C
    25. 8.25 SPI
    26. 8.26 CAN-FD
    27. 8.27 Low-Frequency Sub System (LFSS)
    28. 8.28 RTC_B
    29. 8.29 IWDT_B
    30. 8.30 WWDT
    31. 8.31 Timers (TIMx)
    32. 8.32 Input/Output Diagrams
    33. 8.33 Device Analog Connections
    34. 8.34 Serial Wire Debug Interface
    35. 8.35 Boot Strap Loader (BSL)
    36. 8.36 Device Factory Constants
    37. 8.37 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.6 DMA

The direct memory access (DMA) controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA can be used to move data from ADC conversion memory to SRAM. The DMA reduces system power consumption by allowing the CPU to remain in low power mode, without having to awaken to move data to or from a peripheral.

The DMA in these devices support the following key features:

  • 9 independent DMA transfer channels
    • 5 full-feature channel (DMA0-DMA4), supporting repeated transfer modes
    • 4 basic channels (DMA5-DMA8) supporting single transfer modes
  • Configurable DMA channel priorities
  • Byte (8-bit), short word (16-bit), word (32-bit) and long word (64-bit) and long-long word (128-bit) or mixed byte and word transfer capability
  • Transfer counter block size supports up to 64k transfers of any data type
  • Configurable DMA transfer trigger selection
  • Active channel interruption to service other channels
  • Early interrupt generation for ping-pong buffer architecture
  • Cascading channels upon completion of activity on another channel
  • Stride mode to support data re-organization, such as 3-phase metering applications
  • Gather mode

Table 8-2 DMA Features
FeatureFULLBASIC
Channel#0,1,2,3,45,6,7,8
Repeat ModeYes-
Table & Fill Mode Yes-
Gather ModeYes-
Pre-IRQYes-
Auto EnableYesYes
Long Long (128-bit) TransferYesYes
Stride Mode YesYes
Cascading Channel Support YesYes

Table 8-3 lists the available triggers for the DMA which are configured using the DMATCTL.DMATSEL control bits in the DMA memory mapped registers.

Table 8-3 DMA Trigger Mapping
DMACTL.DMATSELTrigger Source
0Software
1Generic Subscriber (FSUB_0)
2Generic Subscriber (FSUB_1)
3AESADV Publisher 1
4AESADV Publisher 2
5

S0U2 RX Publisher 1

6S0U2 TX Publisher

2

7S0U3 UART RX Publisher 1
8S0U3 TX Publisher 2
9S0U4 RX Publisher 1
10S0U4 TX Publisher 1
11S1U0

RX Publisher 1

12S1U0

TX Publisher 2

13S1U2

RX Publisher 1

14S1U2

TX Publisher 2

15ADC0 DMA Trigger
16ADC1 DMA Trigger
For more details, see the DMA chapter of the MSPM0 G-Series 80MHz Microcontrollers Technical Reference Manual.