SLVSJA8 July   2025 SN74LV8T273-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Noise Characteristics
    7. 5.7 Timing Characteristics
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 Latching Logic with Known Power-Up State
      3. 7.3.3 LVxT Enhanced Input Voltage
        1. 7.3.3.1 Up Translation
        2. 7.3.3.2 Down Translation
      4. 7.3.4 Wettable Flanks
      5. 7.3.5 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Design Requirements
      1. 8.3.1 Power Considerations
      2. 8.3.2 Input Considerations
      3. 8.3.3 Output Considerations
    4. 8.4 Detailed Design Procedure
    5. 8.5 Application Curve
    6. 8.6 Power Supply Recommendations
    7. 8.7 Layout
      1. 8.7.1 Layout Guidelines
      2. 8.7.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.7 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION CONDITION VCC -40°C to 125°C UNIT
MIN MAX
tW Pulse duration CLR low 1.8V 2.7 ns
tW Pulse duration CLK 1.8V 2.7 ns
tSU Setup time Data before CLK edge 1.8V 5.5 ns
tSU Setup time CLR before CLK edge 1.8V 0 ns
tH Hold time Data after CLK edge 1.8V 0 ns
tW Pulse duration CLR low 2.5V 2.7 ns
tW Pulse duration CLK 2.5V 2.7 ns
tSU Setup time Data before CLK edge 2.5V 3.8 ns
tSU Setup time CLR before CLK edge 2.5V 0 ns
tH Hold time Data after CLK edge 2.5V 0 ns
tW Pulse duration CLR low 3.3V 2.7 ns
tW Pulse duration CLK 3.3V 2.7 ns
tSU Setup time Data before CLK edge 3.3V 3.4 ns
tSU Setup time CLR before CLK edge 3.3V 0 ns
tH Hold time Data after CLK edge 3.3V 0 ns
tW Pulse duration CLR low 5V 2.7 ns
tW Pulse duration CLK 5V 2.7 ns
tSU Setup time Data before CLK edge 5V 2.1 ns
tSU Setup time CLR before CLK edge 5V 0 ns
tH Hold time Data after CLK edge 5V 0 ns