SLVSJB7 July   2025 SN74AHC374-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Noise Characteristics
    7. 5.7 Timing Characteristics
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS 3-State Outputs
      2. 7.3.2 Standard CMOS Inputs
      3. 7.3.3 Wettable Flanks
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.8 Switching Characteristics

CL = 50pF; over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See Parameter Measurement Information
PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE VCC -40°C to 125°C UNIT
MIN TYP MAX
fmax CL = 15pF 2V 65 125 MHz
fmax CL = 15pF 3.3V 80 245 MHz
fmax CL = 15pF 5V 130 300 MHz
fmax CL = 50pF 2V 50 120 MHz
fmax CL = 50pF 3.3V 50 170 MHz
fmax CL = 50pF 5V 90 200 MHz
tPLH CLK Q CL = 15pF 2V 7.1 11.6 17.3 ns
tPHL 2V 7.2 12.5 18.9 ns
tPZL OE Q CL = 15pF 2V 6 9.4 13.4 ns
tPZH 2V 6.8 10.5 14.8 ns
tPLZ OE Q CL = 15pF 2V 7.1 9.1 11.7 ns
tPHZ 2V 6.9 9.6 13.3 ns
tPLH CLK Q CL = 15pF 3.3V 5.1 7.4 10.5 ns
tPHL 3.3V 4.8 7.4 11 ns
tPZL OE Q CL = 15pF 3.3V 3.9 5.8 8.2 ns
tPZH 3.3V 4.6 6.7 9.3 ns
tPLZ OE Q CL = 15pF 3.3V 5.3 6.3 7.8 ns
tPHZ 3.3V 4.5 6.2 8.3 ns
tPLH CLK Q CL = 15pF 5V 4.3 5.7 7.8 ns
tPHL 5V 3.7 5.3 7.6 ns
tPZL OE Q CL = 15pF 5V 3.2 4.3 5.8 ns
tPZH 5V 3.8 5 6.7 ns
tPLZ OE Q CL = 15pF 5V 4.8 5.4 6.3 ns
tPHZ 5V 3.3 4.3 5.8 ns
tPLH CLK Q CL = 50pF 2V 8.8 14.3 21.1 ns
tPHL 2V 8.9 14.9 22.3 ns
tPZL OE Q CL = 50pF 2V 7.9 12.1 17.2 ns
tPZH 2V 9 13.5 18.9 ns
tPLZ OE Q CL = 50pF 2V 12.7 14.9 17.7 ns
tPHZ 2V 12.7 15.5 19.2 ns
tPLH CLK Q CL = 50pF 3.3V 6.2 9.2 13.1 ns
tPHL 3.3V 6 9.1 13.4 ns
tPZL OE Q CL = 50pF 3.3V 5.6 7.9 10.8 ns
tPZH 3.3V 6.3 8.9 12.1 ns
tPLZ OE Q CL = 50pF 3.3V 8.9 10 11.5 ns
tPHZ 3.3V 8 9.6 11.7 ns
tPLH CLK Q CL = 50pF 5V 5.2 7 9.6 ns
tPHL 5V 4.8 6.7 9.4 ns
tPZL OE Q CL = 50pF 5V 4.5 5.9 7.9 ns
tPZH 5V 5 6.8 9 ns
tPLZ OE Q CL = 50pF 5V 7 7.6 8.5 ns
tPHZ 5V 5.3 6.4 7.9 ns
tsk(o) CL = 50pF 2V 0.2 0.4 ns
tsk(o) CL = 50pF 3.3V 0.2 0.4 ns
tsk(o) CL = 50pF 5V 0.2 0.4 ns