SLVSJU7A February   2026  – April 2026 SN74LVC1G08B-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5.   5
  6. Pin Configuration and Functions
  7. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 Standard CMOS Inputs
      3. 7.3.3 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  10. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

Revision History

Changes from Revision * (February 2026) to Revision A (April 2026)

  • Updated tpd, CL = 15pF, 1.2V ± 0.1V, maximum from: 41ns to: 48.4nsGo
  • Updated tpd, CL = 15pF, 5.0V ± 0.5V maximum from: 2.7ns to: 2.8nsGo
  • Updated Cpd 1.8V typical from: 21pf to: 13.3pfGo
  • Updated Cpd 2.5V typical from: 24pf to: 14.5pfGo
  • Updated Cpd 3.3V typical from: 26pf to: 16.2pfGo
  • Updated Cpd 5V typical from: 31pf to: 19.9pfGo