SLVSKX1 July   2026 TPSI3052A-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Power Ratings
    5. 6.5 Insulation Specifications
    6. 6.6 Safety Limiting Values
    7. 6.7 Electrical Characteristics
    8. 6.8 Switching Characteristics
    9. 6.9 Insulation Characteristic Curves
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      5. 8.3.5 Power Supply, CE, and EN Sequencing
      6. 8.3.6 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 CDIV1, CDIV2 Capacitance
        2. 9.2.2.2 CVDDP Capacitance
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Start-up Time and Recovery Time
        5. 9.2.2.5 Supplying Auxiliary Current, IAUX From VDDM
        6. 9.2.2.6 VDDM Ripple Voltage
      3. 9.2.3 Application Curves
      4. 9.2.4 Insulation Lifetime
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Links
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.4.2 Layout Example

Figure 9-5 shows a PCB layout example with the signals and key components labeled.

TPSI3052A-Q1 3D PCB ViewFigure 9-5 3D PCB View

Figure 9-6 and Figure 9-7 show the top and bottom layer traces and copper.

TPSI3052A-Q1 Top LayerFigure 9-6 Top Layer
TPSI3052A-Q1 Bottom LayerFigure 9-7 Bottom Layer