SLVSLJ5 Data sheet

SLVSLJ5B March 2026 – September 2026 TCA9846

PRODUCTION DATA

5.6 I²C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
STANDARD MODE
f_scl	I²C clock frequency		0	100	kHz
t_sch	I²C clock high time		4		μs
t_scl	I²C clock low time		4.7		μs
t_sp	I²C spike time		50		ns
t_sds	I²C serial-data setup time		250		ns
t_sdh	I²C serial-data hold time		0⁽¹⁾		μs
t_icr	I²C input rise time			1000	ns
t_icf	I²C input fall time			300	ns
t_ocf	I²C output (SDn) fall time (10pF to 400pF bus)			300	ns
t_buf	I²C bus free time between stop and start		4.7		μs
t_sts	I²C start or repeated start condition setup		4.7		μs
t_sth	I²C start or repeated start condition hold		4		μs
t_sps	I²C stop condition setup		4		μs
t_vdL(Data)	Valid-data time (high to low)⁽²⁾	SCL low to SDA output low valid		1	μs
t_vdH(Data)	Valid-data time (low to high)⁽²⁾	SCL low to SDA output high valid		0.6	μs
t_vd(ack)	Valid-data time of ACK condition	ACK signal from SCL low to SDA output low		1	μs
C_b	I²C bus capacitive load			400	pF
FAST MODE
f_scl	I²C clock frequency		0	400	kHz
t_sch	I²C clock high time		0.6		μs
t_scl	I²C clock low time		1.3		μs
t_sp	I²C spike time		50		ns
t_sds	I²C serial-data setup time		100		ns
t_sdh	I²C serial-data hold time		0⁽¹⁾		μs
t_icr	I²C input rise time		20 + 0.1C_b⁽³⁾	300	ns
t_icf	I²C input fall time		20 + 0.1C_b⁽³⁾	300	ns
t_ocf	I²C output (SDn) fall time (10pF to 400pF bus)		20 + 0.1C_b⁽³⁾	300	ns
t_buf	I²C bus free time between stop and start		1.3		μs
t_sts	I²C start or repeated start condition setup		0.6		μs
t_sth	I²C start or repeated start condition hold		0.6		μs
t_sps	I²C stop condition setup		0.6		μs
t_vdL(Data)	Valid-data time (high to low)⁽²⁾	SCL low to SDA output low valid		1	μs
t_vdH(Data)	Valid-data time (low to high)⁽²⁾	SCL low to SDA output high valid		0.6	μs
t_vd(ack)	Valid-data time of ACK condition	ACK signal from SCL low to SDA output low		1	μs
C_b	I²C bus capacitive load			400	pF
FAST MODE PLUS
f_scl	I²C clock frequency	I²C clock frequency	0	1000	kHz
t_sch	I²C clock high time	I²C clock high time	0.26		μs
t_scl	I²C clock low time	I²C clock low time	0.5		μs
t_sp	I²C spike time	I²C spike time		50	ns
t_sds	I²C serial-data setup time	I²C serial-data setup time	100		ns
t_sdh	I²C serial-data hold time	I²C serial-data hold time	0⁽¹⁾		μs
t_icr	I²C input rise time	I²C input rise time		120	ns
t_icf	I²C input fall time	I²C input fall time	20x (VDD / 5.5V)⁽³⁾	120	ns
t_buf	I²C bus free time between stop and start	I²C bus free time between stop and start	0.5		μs
t_sts	I²C start or repeated start condition setup	I²C start or repeated start condition setup	0.26		μs
t_sth	I²C start or repeated start condition hold	I²C start or repeated start condition hold	0.26		μs
t_sps	I²C stop condition setup	I²C stop condition setup	0.6		μs
t_vdL(Data)	Valid-data time (high to low)⁽²⁾	SCL low to SDA output low valid		0.45	μs
t_vdH(Data)	Valid-data time (low to high)⁽²⁾	SCL low to SDA output high valid		0.45	μs
t_vd(ack)	Valid-data time of ACK condition	ACK signal from SCL low to SDA output low		0.45	μs
C_b	I²C bus capacitive load	I²C bus capacitive load		550	pF

(1) A device internally must provide a hold time of at least 300ns for the SDA signal (referred to the V_IH min of the SCL signal), to bridge the undefined region of the falling edge of SCL.

(2) Data taken using a 1kΩ pullup resistor and 50pF load

(3) Cb = total bus capacitance of one bus line in pF

5.6 I2C Interface Timing Requirements

5.6 I²C Interface Timing Requirements