SLVSLX2 August   2026 SN74UVP1G14

ADVANCE INFORMATION  

  1.   1
  2.   2
  3. Features
  4. Applications
  5. Description
  6. Pin Configuration and Functions
  7. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 CMOS Schmitt-Trigger Inputs
    4. 7.4 Device Functional Modes
  10. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

Features

  • Extended low-voltage operation with 0.63V to 3.6V supply range
  • Extended operating temperature range: –40°C to 125°C
  • Low power consumption
    • Typical ICC = 10nA
    • Typical input leakage II = 3nA
    • Typical output off-state leakage current IOZ = 100nA
    • Typical partial-power-down IOFF 0.2uA
  • 3.6V tolerant input to support down translation
  • Maximum tpd of 9.5ns at 3.3V
  • Drop-in compatible with AUP1G family and VCC extended from 0.8V to 0.63V