SLVSLX2
August 2026
SN74UVP1G14
ADVANCE INFORMATION
1
2
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Balanced CMOS Push-Pull Outputs
7.3.2
CMOS Schmitt-Trigger Inputs
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.1.1
Power Considerations
8.2.1.2
Input Considerations
8.2.1.3
Output Considerations
8.2.2
Detailed Design Procedure
8.2.3
Application Curve
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
Support Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
11.1
Tape and Reel Information
11.2
Mechanical Data
1
Features
Extended low-voltage operation with 0.63V to 3.6V supply range
Extended operating temperature range: –40°C to 125°C
Low power consumption
Typical I
CC
= 10nA
Typical input leakage I
I
= 3nA
Typical output off-state leakage current I
OZ
= 100nA
Typical partial-power-down I
OFF
0.2uA
3.6V tolerant input to support down translation
Maximum t
pd
of 9.5ns at 3.3V
Drop-in compatible with AUP1G family and V
CC
extended from 0.8V to 0.63V