SLVSMW7 July   2026 SN74LVC245B

PRODUCTION DATA  

  1.   1
  2.   2
  3. 1 Features
  4. 2 Applications
  5. 3 Description
  6. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Switching Characteristics
  7. 5 Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Balanced CMOS 3-State Outputs
      2. 6.3.2 Partial Power Down (Ioff)
      3. 6.3.3 CMOS IOs
      4. 6.3.4 Standard CMOS Inputs
      5. 6.3.5 Clamp Diode Structure
      6. 6.3.6 Over-Voltage Tolerant Inputs
    4. 6.4 Device Functional Modes
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information

5 Parameter Measurement Information

Phase relationships between waveforms are selected arbitrarily for the examples listed in the following table. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω, tt ≤ 2.5ns.

The outputs are measured individually with one input transition per measurement.

Table 5-1 3-State Outputs
TEST S1 S2
tPLH, tPHL OPEN OPEN
tPLZ, tPZL CLOSED OPEN
tPHZ, tPZH OPEN CLOSED

Table 5-2 3-State or Open-Drain Outputs
VCC Vt RL CL ΔV VLOAD
1.2V ± 0.1V VCC/2 2kΩ 30pF 0.1V 2×VCC
1.5V ± 0.12V VCC/2 2kΩ 30pF 0.1V 2×VCC
1.8V ± 0.15V VCC/2 1kΩ 30pF 0.15V 2×VCC
2.5V ± 0.2V VCC/2 500Ω 30pF 0.15V 2×VCC
2.7V 1.5V 500Ω 50pF 0.3V 6V
3.3V ± 0.3V 1.5V 500Ω 50pF 0.3V 6V
SN74LVC245B Load Circuit for 3-State Outputs
(1) CL includes probe and test-fixture capacitance.
Figure 5-1 Load Circuit for 3-State Outputs
SN74LVC245B Voltage Waveforms Enable and Disable Times
(1) The greater between tPZL and tPZH is the same as ten.
(2) The greater between tPLZ and tPHZ is the same as tdis.
Figure 5-3 Voltage Waveforms Enable and Disable Times
SN74LVC245B Voltage Waveforms Propagation Delays
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 5-2 Voltage Waveforms Propagation Delays
SN74LVC245B Voltage Waveforms, Input and Output Transition Times
(1) The greater between tr and tf is the same as tt.
Figure 5-4 Voltage Waveforms, Input and Output Transition Times