SLVU437B October   2011  – June 2021

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Performance Specification
    3. 1.3 Modifications
      1. 1.3.1 Fixed Output Operation
      2. 1.3.2 Input and Output Capacitors
      3. 1.3.3 Soft-Start Time
      4. 1.3.4 Loop Response Measurement
  3. 2Setup
    1. 2.1 Input/Output Connector Descriptions
    2. 2.2 Setup
  4. 3TPS621x0EVM-505 Test Results
  5. 4Board Layout
  6. 5Schematic and Bill of Materials
    1. 5.1 Schematic
    2. 5.2 Bill of Materials
  7. 6Revision History

4 Board Layout

This section provides the TPS621x0EVM-505 board layout and illustrations.

GUID-A4A19160-9F80-4118-9C10-771871C03D2A-low.gif Figure 4-1 Assembly Layer
GUID-B2ABFB2E-6EE7-46EF-AABF-3AF15583074E-low.gif Figure 4-2 Top Layer Routing
GUID-F259434C-154A-4D2B-8CD6-F1813270A2EF-low.gif Figure 4-3 Internal Layer-1 Routing
GUID-F259434C-154A-4D2B-8CD6-F1813270A2EF-low.gif Figure 4-4 Internal Layer-2 Routing
GUID-DCA65828-1819-4A65-81B6-487637A11F64-low.gif Figure 4-5 Bottom Layer Routing