SLVUBB4B November   2017  – February 2023

 

  1.   Abstract
  2.   Trademarks
  3. 1 Topologies Window
  4. 2 FET Losses Calculator
  5. 3 Load Step Calculator
  6. 4 Capacitor Current Sharing Calculator
  7. 5 AC/DC Bulk Capacitor Calculator
  8. 6 RCD-Snubber Calculator for Flyback Converters
  9. 7 RC-Snubber Calculator
  10. 8 Output Voltage Resistor Divider
  11. 9 Dynamic Analog Output Voltage Scaling
  12. 10Dynamic Digital Output Voltage Scaling
  13. 11Unit Converter
  14. 12Loop Calculator
    1. 12.1 Inputs
    2. 12.2 Transfer Functions
      1. 12.2.1  Output Impedance Transfer Function
      2. 12.2.2  Transfer Function VMC Buck Power Stage
      3. 12.2.3  Transfer Function CMC Buck Power Stage
      4. 12.2.4  Transfer Function CMC Boost Power Stage
      5. 12.2.5  Transfer Function CMC Inverting Buck-Boost Power Stage
      6. 12.2.6  Transfer Function CMC Forward Power Stage
      7. 12.2.7  Transfer Function CMC Flyback Power Stage
      8. 12.2.8  Transfer Function Closed Loop
        1. 12.2.8.1 Transfer Function Type II Compensation Network
        2. 12.2.8.2 Transfer Function Type II Transconductance Compensation Network
        3. 12.2.8.3 Transfer Function Type III Compensation Network
      9. 12.2.9  Transfer Function Isolated Type II Compensation Network With a Zener Clamp
      10. 12.2.10 Transfer Function Isolated Type II Compensation Network Without a Zener Clamp
  15. 13Filter Designer
    1. 13.1 Impedances
    2. 13.2 Transfer Functions
    3. 13.3 Filter Output Impedance
    4. 13.4 Damping Factor
  16. 14Additional Information
  17. 15Revision History

1 Topologies Window

To start a power supply design with Power Stage Designer, first select a topology from the Topology menu. The window changes and displays the schematic of the selected topology with a set of input fields and various output values. After entering the parameters of the power supply specification, Power Stage Designer suggests a value for the output inductance to stay below the entered current ripple requirement. For isolated topologies, the tool also displays a recommendation for the transformer turns ratio (TTR) based on the selected maximum duty cycle and suggests a value for the magnetizing inductance. Users can enter values of their choice and evaluate their impact on voltage and current waveforms and other parameters like on-time, off-time, and duty cycle.

#SLVUBB49830 shows the main window of Power Stage Designer displaying supported topologies.

GUID-19ECC202-4841-49E5-A043-A4AFB0D34F55-low.png Figure 1-1 Main Window of Power Stage Designer Displaying Supported Topologies
GUID-14A92E4F-ABEC-4FC1-B09E-DFA63E09B767-low.png Figure 1-2 Topology Window for SEPIC

After clicking on one of the yellow highlighted components in the schematic (see #SLVUBB42919), a new window displays the voltage and current waveforms for this specific component (see #SLVUBB45520). Additional information like the minimum and maximum voltage, minimum and maximum current, as well as root mean square (RMS), average, and AC values for the current is also provided in this window. The input voltage can be changed across the entire input voltage range with a slider. For most topologies the load current can be altered in the range of 1% to 100% of the entered output current with a second slider. Some topology models do not support such a wide load current range, thus the load current slider can be changed only in the range of 50% and 100%. The Quasi-resonant Flyback model uses a fixed output power as base for all calculations. That is why the load current slider is not available for this specific topology.

GUID-BBD4C900-5287-42EA-9149-50289A0A2110-low.png Figure 1-3 Graph Window for FET Q1 of a SEPIC Operating in CCM
Note:

All equations used for calculations are ideal, with the only exception that the forward voltage of rectifier and freewheeling diodes is considered. For a collection of the equations behind certain topologies, see the Power Topologies Handbook.