SLVUBY5A March   2021  – July 2021 TPSM63603

 

  1.   Abstract
  2.   Trademarks
  3. 1EVM Setup
  4. 2EVM Connectors and Test Points
  5. 3Test Results
  6. 4PCB Layouts
  7. 5Schematics
  8. 6Bill of Materials
  9. 7Revision History

2 EVM Connectors and Test Points

Wire-loop test points and scope probe sockets are included for digital voltmeters (DVM) or oscilloscope probes to aid in the evaluation of the device. Table 2-1 describes each test point.

Table 2-1 Test Point Descriptions
Test Point(1) Description
VIN S+ Input voltage monitor. Connect the positive lead of a DVM to this point for measuring efficiency.
VIN S- Input ground monitor. Connect the negative lead of a DVM to this point for measuring efficiency.
VOUT S+ Output voltage monitor. Connect the positive lead of a DVM to this point for measuring efficiency, line regulation, and load regulation.
VOUT S- Output ground monitor. Connect the negative lead of a DVM to this point for measuring efficiency, line regulation, and load regulation.
PGND Power ground test points.
VIN Scope (J2) Input voltage scope monitor. Connect an oscilloscope probe to this set of points to measure input ripple voltage.
VOUT Scope (J3) Output voltage scope monitor. Connect an oscilloscope probe to this set of points to measure output voltage ripple and transient response.
EN Enable test point. Monitors the enable signal of the device. Use the ENABLE Control header (J5) to disable the device. If a logic signal is used to control the EN feature, remove the jumper from the J5 header.
ENABLE Control (J5) Enable select jumper. Enable or disable the device using a jumper. When in the ON position, the EN pin is pulled up to VIN directly. If the SYNC feature is to be used, remove the jumper from the J5 header.
SYNC Synchronization test point. Connect a valid clock signal to this test point to synchronize the switching frequency. Remove the ENABLE jumper (J5) when applying a schronization clock signal.
PGOOD Power good test point. Monitors the power good signal of the device. This is an open-drain signal A 49.9-kΩ resistor is connected to this pin and the PG_PU pin on the EVM.
PG_PU PGOOD pullup test point. Apply a voltage to this pin to use as a pullup voltage for the PGOOD signal. A 49.9-kΩ resistor is connected to this pin and the PGOOD pin on the EVM.
(1) Refer to the product data sheet for absolute maximum ratings associated with the features in this table.