SLVUBZ2A September   2020  – December 2020 LM5127-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Applications
    2. 1.2 Features
  3. 2EVM Setup
    1. 2.1 EVM Characteristics
  4. 3EVM Photo
  5. 4Testing Procedures
    1. 4.1 EVM Connectors and Test Points
  6. 5Test Results
    1. 5.1 Efficiency
    2. 5.2 Thermal Performance
    3. 5.3 Steady State
    4. 5.4 Load Transient
    5. 5.5 Line Transient Responses
  7. 6Schematics, PCB Layers, and Bill of Materials
    1. 6.1 Schematics
    2. 6.2 PCB Layers
    3. 6.3 Bill of Materials
  8. 7EVM Modifications
    1. 7.1 Configure Channel 1 as a Buck Controller
      1. 7.1.1 Component Modifications
      2. 7.1.2 CFG/MODE Pin Selection
    2. 7.2 Configure Channel 2 and Channel 3 as a Dual Phase Buck Controller
      1. 7.2.1 Component Modifications
      2. 7.2.2 CFG/MODE Pin Selection
    3. 7.3 EVM Modification Test Setups
  9. 8Revision History

4.1 EVM Connectors and Test Points

Table 4-1 lists the EVM jumper descriptions.

Table 4-1 Jumper Descriptions
JumperNameDescription
J1VCH1AWhen CH1 is configured as a boost controller this jumper is the connection for the input power for the boost controller. When CH1 is configured as a buck controller this is the output voltage for the buck controller
J2VCH1BWhen CH1 is configured as a boost controller this jumper is the connection for the output power for the boost controller. When CH1 is configured as a buck controller this is the input voltage for the buck controller
J3 SS1 Populating this jumper will enable diode emulation mode (DEM) on CH1
J4 PGOOD1/PGOOD2/PGOOD3 Probe points for PGOOD1, PGOOD2, PGOOD3. An external 5 V must be applied between TP10 and TP11 for these signals to be active
J5 VCCX Bias voltage connection to the VCCX pin from one of the output channels on the board. Connecting pin 1 and pin 2 biases the VCCX with VCH1A. This connection is typically made when CH1 is configured as a buck controller. Connecting pin 3 and pin 4 biases the VCCX with VOUT2. Connecting pin 5 and pin 6 biases the VCCX with VOUT3.
J6EN1Input to enable or disable CH1. Connecting pin 1 and pin 2 enables CH1 by connecting the EN1 pin to the BIAS pin. Connecting pin 2 to pin 3 disables CH1 by connecting EN1 to GND.
J7EN2Input to enable or disable CH2. Connecting pin 1 and pin 2 enables CH2 by connecting the EN2 pin to the BIAS pin. Connecting pin 2 to pin 3 disables CH2 by connecting EN2 to GND.
J8EN3Input to enable or disable CH3. Connecting pin 1 and pin 2 enables CH3 by connecting the EN3 pin to the BIAS pin. Connecting pin 2 to pin 3 disables CH3 by connecting EN3 to GND.
J9, J10, J11PGNDPower ground connections for oscilloscope measurements.
J12SYNC/DITHER/VCC_HOLDConfigures the SYNC/Dither/VCC_HOLD pin based on the application specifications. Connecting pin 1 and pin 2 will enable the VCC hold functionality. Connecting a function generator between pin 2 and pin 3 allows for external clock synchronization if C34 is removed and J14 is left open. J14 and J12 should not be populated at the same time.
J13 RES Configuration of the RES pin. Connecting pin 1 and pin 2 enables cycle by cycle peak current limiting with no hiccup mode. Connecting pin 2 and pin 3 latches the channel off until the appropriate enable pin is toggled. If the jumper is left of the hiccup mode time is determined by the value of capacitor connected to the RES pin (C34)
J14 Dither Leaving this jumper and J12 open enables frequency dithering functionality. When pin 1 and pin 2 are connected frequency dithering, external clock synchronization and VCC_HOLD are disabled.
J15CFG/MODEThis pin configures the LM5127 to the appropriate topology and switching mode for the application. For the standard configuration of this EVM the jump should be connected between pin 1 and pin 2 (SKIP) or between pin 5 and pin 6 (FPWM/DEM). See Table 4-3 for more detail on the device configuration.
J16VBUS Input voltage rail of CH2 and CH3 buck controllers. VBUS can be tied to VCH1B by populating R33 with a 0Ω resistor.
J17 VOUT2 Output voltage connection of CH2
J18SS2Populating this jumper will enable diode emulation mode (DEM) on CH2
J19VOUT3Output voltage connection of CH3
J20SS3Populating this jumper will enable diode emulation mode (DEM) on CH3

Table 4-2 lists the EVM test point descriptions.

Table 4-2 Test Point Description
Test PointNameDescription
TP1VCH1APositive voltage probe point for VCH1A
TP2VCH1BPositive voltage probe point for VCH1B
TP3PGNDGround probe point for VCH1B
TP4PGNDGround probe point for VCH1A
TP5VCH1B (+)CH1 loop response positive injection point
TP6VCH1B (-)CH1 loop response negative injection point
TP7DIS/BMOUTDIS/BMOUT pin probe point
TP8SS1SS1 pin probe point
TP9AGNDAGND probe point
TP105V_EXT (+)Positive external 5V connection to pull PGOODx to 5V
TP115V_EXT (-)Negative connection for external 5V PGOOD supply.
TP12VBUSPositive voltage probe point for VBUS
TP13PGNDGround probe point for VBUS
TP14VOUT2Positive voltage probe point for VOUT2
TP15VOUT2(+)CH2 loop response positive injection point
TP16VOUT2(-)CH2 loop response negative injection point
TP17PGNDGround probe point for VOUT2
TP18SS2SS2 pin probe point
TP19VOUT3(+)CH3 loop response positive injection point
TP20VOUT3Positive voltage probe point for VOUT3
TP21VOUT3(-)CH3 loop response negative injection point
TP22PGNDGround probe point for VOUT3
TP23SS3SS3 pin probe point

Table 4-3 lists the LM5127-Q1 pin CFG/MODE connection details (J15).

Table 4-3 CFG/MODE (J15) Connection Details
ConfigurationPin ConnectionCH1CH2CH3Switching Mode
1 (0Ω) 11 to 2BoostSingle BuckSingle BuckSkip Mode
2 (9.53kΩ)3 to 4Buck
3 (19.1kΩ) 15 to 6BoostFPWM/DEM
4 (29.4kΩ)7 to 8Buck
5 (41.2kΩ)9 to 10BoostDual Phase BuckCH1: SkipCH2/CH3: FPWM/DEM
6 (54.9kΩ)11 to 12Buck
7 (71.5kΩ)13 to 14BoostFPWM/DEM
8 (90.9kΩ)15 to 16Buck