SLVUC30 July   2021 TPS1HC100-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2BoosterPack Operation
  4. 3TPS1HC100EVM Schematic
  5. 4Connection Descriptions
  6. 5Current Limit and Current Sense Configuration
  7. 6Transient Protection
  8. 7TPS1HC100EVM Assembly Drawings and Layout
  9. 8Bill Of Materials
  10. 9Appendix - TPL0102-100 Resistance Codes

2 BoosterPack Operation

While the TPS1HC100EVM can be used as a standalone evaluation board without the need of any external microcontroller, the EVM also comes populated with BoosterPack headers to enable easy interface with a Texas Instruments microcontroller. The 40-pin headers of the BoosterPack headers are used, however all signals can be accessed using headers J1 and J2 enabling use with the 20-pin header. Additionally, by populating the "LDO to BP Power" jumper, the user has the ability to power the underlying LaunchPad via the integrated 3.3-V LDO on the TPS1HC100EVM. Table 2-1 contains a list of pins connected to the BoosterPack header.

Table 2-1
BoosterPack PinFunctionNote
J1-13.3-V Power RailDisconnect "LDO to BP Power" if powering from USB.
J1-5Open drain FAULT pin from TPS1HC100B-Q1J13 will control whether FAULT pin is pulled up from the BoosterPack's 3.3-V rail or the 3.3-V onboard LDO of the TPS1HC100EVM
J1-6Current sensing via the SNS pin Resistor controlled either by digital potentiometer U3, potentiometer labeled "SNS", or soldered down resistor R12
J1-9I2C SDA line for onboard TPL0102-100 digipot (controlling the current limit)Pulled up to BoosterPack's 3.3-V rail
J1-10I2C SCL line for onboard TPL0102-100 digipot (controlling the current limit)Pulled up to BoosterPack's 3.3-V rail
J2-5EN to enable VOUTActive high. Can be connected to PWM
J2-6LATCH pin of TPS1HC100B-Q1Controls latching behavior of the TPS1HC100B-Q1. See the device data sheet for details.
J2-7DIAG_EN pin of TPS1HC100B-Q1Enables and disables diagnostics for the TPS1HC100B-Q1. See the device data sheet for details.