SLVUC79A april   2022  – june 2023 TPSI2140-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4.   General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  5. 1Introduction
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
  6. 2Connection Descriptions
  7. 3Test Equipment
  8. 4Recommended Test Setup
    1. 4.1 Waveforms
    2. 4.2 S2 Voltage Divider
  9. 5Schematic
  10. 6PCB Layout
  11. 7Bill of Materials
  12. 8Revision History

2 Connection Descriptions

Table 2-2 shows an overview of the input/output connectors. Table 2-2 shows the test points and jumpers.

Table 2-1 Input and Output Connector Descriptions
Connector Label Description
J1 HV+ Secondary side positive input
J2 S2 Voltage sense output
J3 HV– Secondary side negative input
J4 VDD Primary

Side supply
J5 GND Primary

Side GND
J6 EN_EXTERNAL External

Enable signal
Table 2-2 Test Point and Jumper Descriptions
Test Point, Jumper Label Description
TP1 VDD Primary side supply test point
TP2 EN EN test point
TP4 GND Primary side ground test point
TP5 S1 Secondary side HV+ voltage after resistor chain
TP6 SM Thermal Pin
TP7 S2 Voltage sense output test point
TP8 HV- HV– secondary side test point
J7 EN_EXTERNAL/EN/VDD Connects VDD to EN,

or EN to EN_EXT. Allows for external enable signal to be used instead of EN being signaled by VDD