SLVUCD2 January 2022 TPS65917-Q1
3.7 SWOFF_HWRST
This section describes whether each reset type is configured to generate a HWRST or SWORST.
- Hardware reset (HWRST)A hardware reset occurs when any OFF request is configured to generate a hardware reset. This reset triggers a transition to the OFF state from either the ACTIVE or SLEEP state (execute either the ACT2OFF or SLP2OFF sequence).
- Switch-off reset (SWORST)A switch-off reset occurs when any OFF request is configured to not generate a hardware reset.
This reset acts as the HWRST, except only the SWO registers are reset. The
device enters the OFF state, from either ACTIVE or SLEEP, and therefore
executes the ACT2OFF or SLP2OFF sequence.
The power resource control registers for SMPS and LDO voltage levels and operating mode control are in SWORST domain. Additionally, some registers control the 32-kHz, REGENx and SYSENx, watchdog, and VSYS_MON comparator. This list is indicative only.
Figure 3-3 Reset Levels versus RegistersTable 3-13 SWOFF_HWRST OTP Settings
| REGISTER | BIT | DESCRIPTION | 0x30, 0x31, 0x32, 0x33 VALUE | ||
|---|---|---|---|---|---|
| SWOFF_HWRST | PWRON_LPK | Define if PWRON long key press is causing HWRST or SWORST | 1: HWRST | ||
| PWRDOWN | Define if PWRDOWN pin is causing HWRST or SWORST | 0: SWORST | |||
| WTD | Define if watchdog expiration is causing HWRST or SWORST | 1: HWRST | |||
| TSHUT | Define if thermal shutdown is causing HWRST or SWORST | 1: HWRST | |||
| RESET_IN | Define if RESET_IN pin is causing HWRST or SWORST | 1: HWRST | |||
| SW_RST | Define if register bit is causing HWRST or SWORST | 1: HWRST | |||
| VSYS_LO | Define if VSYS_LO is causing HWRST or SWORST | 1: HWRST | |||
| GPADC_SHUTDOWN | Define if GPADC event is causing HWRST or SWORST | 0: SWORST | |||