SLVUCI0 May   2022 TPS274C65

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Compatibility Across Silicon Versions
  5. 3BoosterPack™ Plug-in Module Operation
  6. 4TPS274C65EVM Schematic
  7. 5Connection Descriptions
  8. 6TPS274C65EVM Assembly Drawings and Layout
  9. 7Bill of Materials

5 Connection Descriptions

Table 5-1 shows the test points populated on the board as well as the signal connectors.

Table 5-1 Connections and Test Points
Connector and Test PointDescription
J2, TP1Supply Voltage VS
J3, TP2VDD voltage. Connect a supply if internal regulator is disabled
J4, TP3Output voltage 1 (VOUT1)
TP4RCB1 signal
J7, TP9Output voltage 2 (VOUT2)
TP10RCB2 signal
J8, TP13Output voltage 3 (VOUT3)
TP15RCB3 signal
J9, TP17Output voltage 4 (VOUT4)
TP19RCB4 signal
J5, J10 BoosterPack plug-in module headers. Can be used to connect to TI microcontroller directly, or use jumpers to pair with other microcontrollers.
J6, J11, TP5, TP7, TP8, TP11, TP14, TP20, TP24, TP27Ground
TP18 FAULT Signal
TP22 ADDCFG pin
TP23 SCLK pin on IC
TP25 SDI pin on IC
TP26 SDO pin on IC
TP28 CS pin on IC
TP29 ISNS pin on IC

Table 5-2 shows the relevant configuration jumpers of the TPS274C65EVM as well as the associated values. Please refer to the TPS274C65 data sheet for detailed information on each pin's functionality.

Please note that a white mark on the jumper silkscreen is reflecting the position 1 of the jumper.

Table 5-2 Jumper Configurations
JumperFunction/Settings
J1Connect 1 and 2 to disable on-board buck converter; connect 2 and 3 to enable on-board buck converter.
J12Connect 1 and 2 to use fixed 1-kΩ resistor; connect 2 and 3 to use on-board potentiometer.
J13Disconnect to use the internal regulator; do not use external VDD. Connect to disable the internal regulator; use external VDD in this case.
J14Connect to enable SPI communications.
J15Connect 1 and 2 to enable daisy chain mode SPI communication; connect 2 and 3 to use addressable SPI.
J16Connect 2 and 3 to power VDD using internal buck converter; connect 1 and 2 to power VDD with microcontroller voltage output; leave open when using internal regulator.
J17Connect 2 and 3 if using addressable SPI; connect 1 and 2 for every other EVM if using multiple EVMs in daisy chain mode.
J18Connect 2 and 3 if using addressable SPI; connect 1 and 2 for every other EVM if using multiple EVMs in daisy chain mode.
J19, J20, J21, J22Connect to bypass the RCB FETs; leave open for reverse current blocking.

Please refer to Table 5-3 for ADDCFG DIP switch configuration.

Table 5-3 ADDCFG DIP Switch Configurations
DIP Switch Position Resistor Value ADDCFG Code
1 110 kΩ 111
2 78.7 kΩ 110
3 59 kΩ 101
4 44.2 kΩ 100
5 31.6 kΩ 011
6 23.7 kΩ 010
7 17.8 kΩ 001
8 13.3 kΩ 000