SLVUCK2A january   2023  – april 2023 TPS7H3302-SEP

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Description
    1. 2.1 Related Information
    2. 2.2 Typical Applications
    3. 2.3 Features
    4. 2.4 Performance Specification Summary
  5. 3Test Setup
    1. 3.1 Equipment
      1. 3.1.1 Power Supplies
      2. 3.1.2 Load #1
    2. 3.2 EVM Connectors and Test Points
    3. 3.3 Testing Procedure
      1. 3.3.1 EVM Bode Plot Measurement Setup
      2. 3.3.2 EVM Transient Test
  6. 4Board Layout
  7. 5Schematic
  8. 6Bill of Materials
  9. 7Related Documentation
  10. 8Revision History

Description

The TPS7H3302-SEP is a radiation-tolerant double data rate (DDR) ±3 A termination regulator with built-in VTTREF buffer. The regulator is specifically designed to provide a complete, compact, low-noise device for space DDR termination applications such as single board computers, solid state recorders, and payload processing.

The TPS7H3302-SEP supports DDR VTT termination applications using DDR, DDR2, DDR3, and DDR4. The fast transient response of the TPS7H3302-SEP VTT regulator allows for a very stable supply during read and write conditions. During transients, the fast tracking feature of the VTTREF supply minimizes any voltage offset between VTT and VTTREF. To enable simple power sequencing, both an enable input and a power-good output (PGOOD) have been integrated into the TPS7H3302-SEP. The open-drain output of the PGOOD terminal is compatible with being tied to other open-drain outputs, which facilitates the monitoring of a group supplies; such that a solitary GPIO pin can detect when all supplies are in regulation. The enable signal also discharges VTT during suspend to RAM (S3) power down mode.