SLVUD18A November   2024  – April 2026

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5. 1.5 General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  7. 2Hardware
    1. 2.1 Test Equipment
    2. 2.2 Connection Descriptions
  8. 3Implementation Results
    1. 3.1 Recommended Test Setup
      1. 3.1.1 Waveforms
  9. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  10. 5Additional Information
    1. 5.1 Trademarks
  11. 6Revision History

2.2 Connection Descriptions

Table 2-3 shows an overview of the input/output connectors. Table 2-2 shows the test points and jumpers.

Table 2-1 Input and Output Connector Descriptions
ConnectorLabelDescription
J1LDO_INPUT+LDO input for connecting external power supply
J2GNDPrimary side GND
J4HVSecondary side High Voltage input
J8GNDSecondary side GND
Table 2-2 Test Point and Jumper Descriptions
Test Point, JumperLabelDescription
J3LDOConnects LDO output to VDD supply rail
J5CEConnects Chip Enable input signal to VDD or external input when left unconnected
J6DIV0Connects DIV0 (Divider Ratio input) to 5V/GND or float when left unconnected
J7REFConnects REF (Reference voltage input) to 2.05V/GND for Bi-directional/Unidirectional voltage monitoring modes
J9DIV1Connects DIV1 (Divider Ratio input) to 5V/GND or float when left unconnected
TP1

AOUT

HV sense signal Analog Output

TP2

VDD

Primary side supply test point

TP3

HV

HV secondary side test point

TP4

CE

CE primary side test point, can be used to drive CE externally when J5 is disconnected

TP5

DIV0

DIV0 select voltage test point

TP7

GND

Primary side GND test point
TP8

REF

REF select voltage test point

TP9

DIV1

DIV1 select voltage test point

TP10

GND

Secondary side GND test point