SLVUD82 July   2026 TPS65214

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521403 Power Sequence and Example Block Diagram
  6. 3NVM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Low Power Mode
  7. 4Revision History

3.2 Enable Settings

This section describes the PMIC rails that are enabled in Active and Standby state. Any rail that is disabled by default has the option to be enabled through I2C once the device is in Active state and I2C communication is available. The transition between Active and Standby state can be triggered by hardware (when MODE/STBY pin is configured as STBY) or by software (register field: STBY_I2C_CTRL).

Table 3-2 ACTIVE state
PMIC RailRegister AddressField NameValueDescription
BUCK10x02BUCK1_EN0x1Enabled
BUCK20x02BUCK2_EN0x1Enabled
BUCK30x02BUCK3_EN0x1Enabled
LDO10x02LDO1_EN0x1Enabled
LDO20x02LDO2_EN0x1Enabled
GPO0x1EGPO_EN0x1GPO1 enabled. The output state is Hi-Z.
GPIO0x1EGPIO_EN0x0GPIO not enabled. The output state is low.
Table 3-3 STANDBY (STBY) state
PMIC RailRegister AddressField NameValueDescription
BUCK10x21BUCK1_STBY_EN0x1Enabled in STBY Mode
BUCK20x21BUCK2_STBY_EN0x1Enabled in STBY Mode
BUCK30x21BUCK3_STBY_EN0x1Enabled in STBY Mode
LDO10x21LDO1_STBY_EN0x1Enabled in STBY Mode
LDO20x21LDO2_STBY_EN0x1Enabled in STBY Mode
GPO0x22GPO_STBY_EN0x1Enabled in STBY Mode
GPIO0x22GPIO_STBY_EN0x0Not enabled in STBY Mode
nRSTOUT 0x22 nRSTOUT_STBY_CONFIG 0x1 nRSTOUT de-asserted in STBY Mode