SLVUDL3 November   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Setup
      1. 2.1.1 Connector Descriptions
      2. 2.1.2 Hardware Setup
    2. 2.2 Modifications
      1. 2.2.1 Input and Output Capacitors
      2. 2.2.2 Feedforward Capacitor
  9. 3Hardware Design Files
    1. 3.1 Schematic
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  10. 4Additional Information
    1. 4.1 Trademarks
  11. 5Related Documentation

2.1.1 Connector Descriptions

J1, Pin 1 and 2 – VINPositive input voltage connection from the input supply for the EVM
J1, Pin 3 and 4 – S+/S–Input voltage sense connections. Measure the input voltage at this point.
J1, Pin 5 and 6 – GNDInput return connection from the input supply for the EVM
J2, Pin 1 and 2 – VOUTPositive output voltage connection
J2, Pin 3 and 4 – S+/S–Output voltage sense connections. Measure the output voltage at this point.
J2, Pin 5 and 6 – GNDOutput return connection
JP1 – ENEN pin jumper. Place the supplied jumper across ON and EN to turn on the IC. Place the jumper across OFF and EN to turn off the IC.
JP2 – MODE/SYNCMODE/SYNC pin jumper. Place the supplied jumper across PWM and MODE/SYNC to operate the device in forced PWM mode. Place the jumper across PFM and MODE/SYNC to operate the device in PFM/PWM mode
JP3 – PG/GNDThe PG output appears on pin 1 of this header with a convenient ground on pin 2
JP4 – PG Pullup VoltagePG pin pullup voltage jumper. Place the supplied jumper on JP4 to connect the PG pin pullup resistor to the input voltage. Alternatively, the jumper can be removed and a different voltage can be supplied on pin 1 to pull up the PG pin to a different level. This externally applied voltage must remain below Vin + 0.3V.
JP5 – SW Test pointThis test point is the SW node test point. Use only if needed. Can be left floating.