SLYT793A may   2020  – may 2020 LM61460-Q1

 

  1.   1
  2. 1 Introduction
  3. 2 Managing Thermals with Flip-chip Packages
  4. 3 Board Construction Influence
  5. 4 Copper Area and Thermals
  6. 5 Estimating a Converter’s Junction Temperature
  7. 6 Challenges with Measuring Converter Junction Temperature
  8. 7 Further Thermal Optimization at the IC Level
  9. 8 Conclusion
  10. 9 References
  11. 10Related Web Sites
    1. 10.1 General Information:
    2. 10.2 Product Information:

5 Estimating a Converter’s Junction Temperature

The simulated RθJA from a Joint Electron Device Engineering Council (JEDEC) standard board is found in a converter’s data sheet. JEDEC boards often have very small traces that are not ideal for thermal conductivity (Figure 6). Landing pad-to-trace or copper-plane connections allow for heat conduction. In practice, the connections will be made to large copper areas in the mid layers, making the simulated RθJA too conservative.

To estimate a board’s RθJA experimentally, note the rise in IC case temperature (∆T) at a given power condition. A preferable power condition would be one where low loss would occur in a buck converter’s output inductor, but high-enough power loss exists to establish a gradient with a thermal camera for measurement. Even with proper mounting, a thermocouple can often give an inaccurate temperature measurement of the top case because of its heat sinking tendency. From the measured efficiency, η, (at the same ambient temperature), Equation 1 calculates the power loss (∆P) in the converter and board RθJA as:

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GUID-A59E7A8E-A5BB-4CAA-9A12-3B9FDAA2E974-low.png Figure 6 A High Thermal-resistance JEDEC Board Used for Characterizing a Device’s RθJA

While the efficiency calculation does include inductor losses (which do not lead to a direct rise in the IC temperature), heat sharing does occur between the inductor and IC. The converter is not the only source of heat. The RθJA approximation becomes more accurate with inductors that have lower losses or lower bias current. An exercise to further improve this estimate could entail forward-biasing either of the power stage’s body diodes to heat up the IC, eliminating inductor influence. The diode’s voltage drop and bias current would then be used for power loss (∆P).

It is critical to consider the converter’s FET temperature coefficient in the calculations. The FET’s drain-to-source on-resistance [RDS(on)] will be worst at the design’s maximum ambient temperature (TA_max). Increased FET RDS(on) causes efficiency to degrade at a high ambient temperature (ηH). Equation 2 expresses the converter power loss ∆PH at the design’s maximum rated ambient temperature:

∆PH =(1− ηH) × PIN (2)

Equation 3 estimates the worst-case junction temperature at the maximum ambient temperature, TA_max

TJ = TA_max + RθJA × ∆PH (3)