1 How increased power density reduces solution size while meeting EMI requirements

The design of isolated bias supplies often involves balancing multiple constraints: board space, thermal performance, and electrical isolation. In applications such as electric vehicle traction systems or data center power architectures, you must provide isolation between high-voltage domains (often ≥800V) and low-voltage control circuits.

Traditional designs implement isolated bias supplies using a discrete flyback converter topology. In these implementations, the transformer is typically the largest component on the printed circuit board (PCB), limiting the achievable power density and increasing solution height.

Isolated bias power modules with IsoShield technology address high power density to meet optimized size requirements in system design by incorporating a planar transformer directly inside the package (as shown in Figure 1), and by using a multiple-chip solution with proprietary bonding connections to create a very compact isolated module.

The mid-voltage UCC34141-Q1 and low-voltage UCC33420-Q1 deliver approximately 1.5W of isolated output power – the former in a 5.85mm-by-7.50mm-by-2.65mm small outline integrated circuit (SOIC) package, the latter in a 4mm-by-5mm-by-1mm very, very small outline, no-lead (WSON) package.

By integrating the transformer and switching elements, these power modules can reduce bias-supply solution area approximately 70% compared to discrete flyback implementations and >35% compared to previous integrated transformer solutions. These reductions translate into power-density improvements >300%.

In addition to footprint reduction, the vertical profile is significantly reduced. Removing the discrete transformer – the tallest component in conventional designs – enables module heights as low as 1mm, which is particularly beneficial in space-constrained applications. Figure 2 shows the solution area reduction associated with moving from a discrete flyback converter implementation (on the left) to a fully integrated solution (on the right).

Thermal performance and electromagnetic interference (EMI) are often concerns with high-density solutions. However, optimized packaging and internal layout can improve thermal dissipation as much as 30% compared to previous modules while maintaining compliance with Comité International Spécial des Perturbations Radioélectriques (CISPR) 25 and CISPR 32 standards, using only minimal filtering (Figure 3).

Designing an EMI solution for a standard isolated bias supply is a nontrivial task. Balancing costly filtering components with the unique filtering needs of a discrete implementation takes experience, time and testing. The nature of an integrated solution means that the filtering needs are much more standardized. TI has taken advantage of this fact by developing application notes that describe how to implement EMI solutions that will pass CISPR standards.

The layout shown in Figure 4 with the solution and small filter size meets the CISPR 25 Class 5 requirement. When combined with a few layout techniques, there are only a few additional bill-of-material components needed to pass CISPR 25 Class 5. In this example we use the highlighted capacitors, inductors, and ferrite beads.

Several layout techniques can further reduce the number of filtering components. Placing high-frequency filtering capacitors C1 and C7 very close to the IC minimizes high-frequency noise. Removing any copper beneath the filtering inductors and ferrite beads minimizes leakage through parasitics, and extending the ground plane on the bottom layer of the printed circuit board creates a Faraday cage.