SNAS828A february   2022  – june 2023 LMK1D1208I

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fail-Safe Input
      2. 9.3.2 Input Stage Configurability
      3. 9.3.3 Dual Output Bank
      4. 9.3.4 I2C
        1. 9.3.4.1 I2C Address Assignment
      5. 9.3.5 LVDS Output Termination
      6. 9.3.6 Input Termination
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Enable Control
      2. 9.4.2 Bank Input Selection
      3. 9.4.3 Bank Mute Control
      4. 9.4.4 Output Enable Control
      5. 9.4.5 Output Amplitude Selection
    5. 9.5 Programming
    6. 9.6 Register Maps
      1. 9.6.1 LMK1D1208I Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

6 Pin Configuration and Functions

GUID-20210716-CA0I-QVTR-7MQD-LWKVCMPHRVPR-low.svgFigure 6-1 LMK1D1208I: RHA Package 40-Pin VQFN (Top View)
Table 6-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMELMK1D1208I
DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT
IN0_P, IN0_N12, 13IPrimary: Differential input pair or single-ended input
IN1_P, IN1_N8, 9ISecondary: Differential input pair or single-ended input.
I2C PROGRAMMING
SDA5I/OI2C data
SCL6II2C clock
IDX015I,S,PUI2C address bit[0]. This is a 2-level input that is decoded in conjunction with pin 15 to set the I2C address. It has internal 670-kΩ pullup.
IDX116I,S, PUI2C address bit[1]. This is a 2-level input that is decoded in conjunction with pin 16 to set the I2C address. It has internal 670-kΩ pullup.
BIAS VOLTAGE OUTPUT
VAC_REF0, VAC_REF114, 10OBias voltage output for capacitive coupled inputs. If used, TI recommends using a 0.1-µF capacitor to GND on this pin.
DIFFERENTIAL CLOCK OUTPUT
OUT0_P, OUT0_N18, 19ODifferential LVDS output pair number 0
OUT1_P, OUT1_N22, 23ODifferential LVDS output pair number 1
OUT2_P, OUT2_N24, 25ODifferential LVDS output pair number 2
OUT3_P, OUT3_N28, 29ODifferential LVDS output pair number 3
OUT4_P, OUT4_N32, 33ODifferential LVDS output pair number 4
OUT5_P, OUT5_N34, 35ODifferential LVDS output pair number 5
OUT6_P, OUT6_N38, 39ODifferential LVDS output pair number 6
OUT7_P, OUT7_N2, 3ODifferential LVDS output pair number 7
SUPPLY VOLTAGE
VDD11, 20, 40PDevice power supply (1.8 V, 2.5 V, or 3.3 V)
GROUND
DAPDAPGDie Attach Pad. Connect to the printed circuit board (PCB) ground plane for heat dissipation.
NO CONNECT
NC1, 4, 7, 17, 21, 26, 27, 30, 31, 36, 37—No connection. Leave floating.
(1) The definitions below define the I/O type for each pin.
  • I = Input
  • O = Output
  • I / O = Input / Output
  • PU = Internal 670-kΩ Pullup
  • S = Hardware Configuration Pin
  • P = Power Supply
  • G = Ground