SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address 0005001C – Loop 4 DPWM Event 4 Register
Address 0007001C – Loop 3 DPWM Event 4 Register
Address 000A001C – Loop 2 DPWM Event 4 Register
Address 000D001C – Loop 1 DPWM Event 4 Register
17 | 0 |
EVENT4 |
R/W-00 0000 0111 0000 0000 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
17-0 | EVENT4 | R/W | 00 0000 0111 0000 0000 | Configures the location of Event 4. Value equals number of PCLK clock periods in Bits 17:4 and number of high resolution clock phases of PCL in Bits 3:0. |