2 Simulation Setup

The simulations will be done using Keysight ADS with the TI DS90LV011A IBIS model (ds90lv001atmf.ibs) that can be downloaded from the URL: https://www.ti.com/lit/zip/snlm047.

Figure 2-1 Simulation Block Diagram

Figure 2-2 Schematic Breakdown

• R₁, R₂, & R₃ make up the resistor network that needs to be created to interface between LVDS and Sub-LVDS. Each differential pair will be made up of these three resistors.
• R_T is the value of the termination resistor for devices that contain internal termination (100Ω will be used for this simulation).
• R_E is the equivalent resistance of all the resistors in the resistor network
  Note: The Thevenin resistance of these resistors must be approximately 50Ω if the device does or does not contain internal termination; this ensures that the circuit will have a 100Ω equivalent termination resistance between the transmitter and receiver for both differential pairs. The appropriate formulas for each scenario can be seen in the sections below.
• V_A is equivalent to the fixed common mode voltage (V_CMF) of the LVDS driver output (1.2 V will be used for this simulation).
• V_OD is the output differential voltage from the LVDS driver.
  • The values used can be obtained from the “Electrical Characteristics” section of the data sheet for your specific device.
  • For more information, see the DS90LV011A 3V LVDS Single High Speed Differential Driver Data Sheet.

Figure 2-3 DS90LV011A Data Sheet Electrical Characteristics

• V_B is equivalent to the fixed common mode voltage (V_CMF) of typical Sub-LVDS driver outputs (0.9V will be used for this simulation).
• V_ID is the output differential voltage of a Sub-LVDS driver. The goal of the simulation is to obtain a value in the operating range for Sub-LVDS transmitters.
  • The values for a Sub-LVDS driver output can be seen in Table 2-1.
  • The values for a Sub-LVDS receiver input can be seein in Table 2-2.