SNLA467 July   2024 TDP2004

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Access Methods
    1. 2.1 Pin-Strap Mode
    2. 2.2 SMBus, I2C Primary Mode
    3. 2.3 SMBus, I2C Secondary Mode
  6. 3Register Mapping
    1. 3.1 Shared Registers
    2. 3.2 Channel Registers
  7. 4RX Equalization Control Settings
  8. 5Flat-Gain
  9. 6RX Equalization and Flat Gain Selection Matrix
  10. 7TDP2004 Programming Example
    1. 7.1 PD Control Through Register Programming
    2. 7.2 Broadcast Channel CTLE Index or Flat Gain Selection Through Register Programming (CTLE Index 2, Flat Gain 0dB)
    3. 7.3 Individual Channel CTLE Index or Flat Gain Selection Through Register Programming (CTLE Index 2, Flat Gain 0dB)
  11. 8Summary
  12. 9References

3.1 Shared Registers

Table 3-1 General Registers (Offset = 0xE2)
BitFieldTypeResetDescription
7RESERVEDR0x0Reserved
6rst_i2c_regsR/W/SC0x0Device reset control: Reset all I2C registers to default values (self-clearing).
5rst_i2c_masR/W/SC0x0Reset I2C Primary (self-clearing).
4-1RESERVEDR0x0Reserved
0frc_eeprm_rdR/W/SC0x0Override MODE and READ_EN_N status to force manual EEPROM configuration load.
Table 3-2 EEPROM_Status Register (Offset = 0xE3)
BitFieldTypeResetDescription
7eecfg_cmpltR0x0EEPROM load complete.
6eecfg_failR0x0EEPROM load failed.
5eecfg_atmpt_1R0x0Number of attempts made to load EEPROM image.
4eecfg_atmpt_0R0x0
3eecfg_cmpltR0x0EEPROM load complete 2.
2eecfg_failR0x0EEPROM load failed 2.
1eecfg_atmpt_1R0x0Number of attempts made to load EEPROM image 2.
0eecfg_atmpt_0R0x0
Table 3-3 DEVICE_ID0 Register (Offset = 0xF0)
BitFieldTypeResetDescription
7-4RESERVEDR0x0Reserved
3device_id0_3R0x0Device ID0 [3:1]: 011
2device_id0_2R0x1
1device_id0_1R0x1
0RESERVEDRXReserved
Table 3-4 DEVICE_ID1 Register (Offset = 0xF1)
BitFieldTypeResetDescription
7device_id[7]R0x0Device ID 0010 1001:

TDP2004

6device_id[6]R0x0
5device_id[5]R0x1
4device_id[4]R0x0
3device_id[3]R0x1
2device_id[2]R0x0
1device_id[1]R0x0
0device_id[0]R0x0