SNLS603 Data sheet

SNLS603D December 2020 – April 2025 DP83TG720R-Q1

PRODUCTION DATA

7.6.2 DP83TG720 Registers

Table 7-22 lists the memory-mapped registers for the DP83TG720 registers. All register offset addresses not listed in Table 7-22 should be considered as reserved locations and the register contents should not be modified.

Table 7-22 DP83TG720 Registers

Offset	Acronym	Section
0h	BMCR	Section 7.6.2.1
1h	BMSR	Section 7.6.2.2
2h	PHYID1	Section 7.6.2.3
3h	PHYID2	Section 7.6.2.4
Dh	REGCR	Section 7.6.2.5
Eh	ADDAR	Section 7.6.2.6
10h	MII_REG_10	Section 7.6.2.7
11h	MII_REG_11	Section 7.6.2.8
12h	MII_REG_12	Section 7.6.2.9
13h	MII_REG_13	Section 7.6.2.10
16h	MII_REG_16	Section 7.6.2.11
18h	MII_REG_18	Section 7.6.2.12
19h	MII_REG_19	Section 7.6.2.13
1Eh	MII_REG_1E	Section 7.6.2.14
1Fh	MII_REG_1F	Section 7.6.2.15
180h	LSR	Section 7.6.2.16
18Bh	LPS_CFG2	Section 7.6.2.17
18Ch	LPS_CFG3	Section 7.6.2.18
18Eh	LPS_STATUS	Section 7.6.2.19
30Fh	TDR_TC12	Section 7.6.2.20
405h	A2D_REG_05	Section 7.6.2.21
41Eh	A2D_REG_30	Section 7.6.2.22
428h	A2D_REG_40	Section 7.6.2.23
429h	A2D_REG_41	Section 7.6.2.24
42Ch	A2D_REG_44	Section 7.6.2.25
42Fh	A2D_REG_47	Section 7.6.2.26
430h	A2D_REG_48	Section 7.6.2.27
442h	A2D_REG_66	Section 7.6.2.28
450h	LEDS_CFG_1	Section 7.6.2.29
451h	LEDS_CFG_2	Section 7.6.2.30
452h	IO_MUX_CFG_1	Section 7.6.2.31
453h	IO_MUX_CFG_2	Section 7.6.2.32
456h	IO_CONTROL_3	Section 7.6.2.33
45Dh	SOR_VECTOR_1	Section 7.6.2.34
45Eh	SOR_VECTOR_2	Section 7.6.2.35
468h	MONITOR_CTRL2	Section 7.6.2.36
46Ah	MONITOR_CTRL4	Section 7.6.2.37
47Bh	MONITOR_STAT1	Section 7.6.2.38
510h	RS_DECODER	Section 7.6.2.39
52Bh	TRAINING_RX_STATUS_7	Section 7.6.2.40
543h	LINK_QUAL_1	Section 7.6.2.41
544h	LINK_QUAL_2	Section 7.6.2.42
545h	LINK_DOWN_LATCH_STAT	Section 7.6.2.43
547h	LINK_QUAL_3	Section 7.6.2.44
548h	LINK_QUAL_4	Section 7.6.2.45
552h	RS_DECODER_FRAME_STAT_2	Section 7.6.2.46
553h	RS_DECODER_FRAME_STAT_3	Section 7.6.2.47
600h	RGMII_CTRL	Section 7.6.2.48
601h	RGMII_FIFO_STATUS	Section 7.6.2.49
602h	RGMII_DELAY_CTRL	Section 7.6.2.50
608h	SGMII_CTRL_1	Section 7.6.2.51
60Ah	SGMII_STATUS	Section 7.6.2.52
60Ch	SGMII_CTRL_2	Section 7.6.2.53
60Dh	SGMII_FIFO_STATUS	Section 7.6.2.54
618h	PRBS_STATUS_1	Section 7.6.2.55
619h	PRBS_CTRL_1	Section 7.6.2.56
61Ah	PRBS_CTRL_2	Section 7.6.2.57
61Bh	PRBS_CTRL_3	Section 7.6.2.58
61Ch	PRBS_STATUS_2	Section 7.6.2.59
61Dh	PRBS_STATUS_3	Section 7.6.2.60
61Eh	PRBS_STATUS_4	Section 7.6.2.61
620h	PRBS_STATUS_6	Section 7.6.2.62
622h	PRBS_STATUS_8	Section 7.6.2.63
623h	PRBS_STATUS_9	Section 7.6.2.64
624h	PRBS_CTRL_4	Section 7.6.2.65
625h	PRBS_CTRL_5	Section 7.6.2.66
626h	PRBS_CTRL_6	Section 7.6.2.67
627h	PRBS_CTRL_7	Section 7.6.2.68
628h	PRBS_CTRL_8	Section 7.6.2.69
629h	PRBS_CTRL_9	Section 7.6.2.70
62Ah	PRBS_CTRL_10	Section 7.6.2.71
638h	CRC_STATUS	Section 7.6.2.72
639h	PKT_STAT_1	Section 7.6.2.73
63Ah	PKT_STAT_2	Section 7.6.2.74
63Bh	PKT_STAT_3	Section 7.6.2.75
63Ch	PKT_STAT_4	Section 7.6.2.76
63Dh	PKT_STAT_5	Section 7.6.2.77
63Eh	PKT_STAT_6	Section 7.6.2.78
871h	SQI_REG_1	Section 7.6.2.79
874h	DSP_REG_74	Section 7.6.2.80
875h	DSP_REG_75	Section 7.6.2.81
1000h	PMA_PMD_CONTROL_1	Section 7.6.2.82
1007h	PMA_PMD_CONTROL_2	Section 7.6.2.83
1009h	PMA_PMD_TRANSMIT_DISABLE	Section 7.6.2.84
100Bh	PMA_PMD_EXTENDED_ABILITY2	Section 7.6.2.85
1012h	PMA_PMD_EXTENDED_ABILITY	Section 7.6.2.86
1834h	PMA_PMD_CONTROL	Section 7.6.2.87
1900h	PMA_CONTROL	Section 7.6.2.88
1901h	PMA_STATUS	Section 7.6.2.89
1902h	TRAINING	Section 7.6.2.90
1903h	LP_TRAINING	Section 7.6.2.91
1904h	TEST_MODE_CONTROL	Section 7.6.2.92
3900h	PCS_CONTROL	Section 7.6.2.93
3901h	PCS_STATUS	Section 7.6.2.94
3902h	PCS_STATUS_2	Section 7.6.2.95
3904h	OAM_TRANSMIT	Section 7.6.2.96
3905h	OAM_TX_MESSAGE_1	Section 7.6.2.97
3906h	OAM_TX_MESSAGE_2	Section 7.6.2.98
3907h	OAM_TX_MESSAGE_3	Section 7.6.2.99
3908h	OAM_TX_MESSAGE_4	Section 7.6.2.100
3909h	OAM_RECEIVE	Section 7.6.2.101
390Ah	OAM_RX_MESSAGE_1	Section 7.6.2.102
390Bh	OAM_RX_MESSAGE_2	Section 7.6.2.103
390Ch	OAM_RX_MESSAGE_3	Section 7.6.2.104
390Dh	OAM_RX_MESSAGE_4	Section 7.6.2.105
7200h	AN_CFG	Section 7.6.2.106

Complex bit access types are encoded to fit into small table cells. Table 7-23 shows the codes that are used for access types in this section.

Table 7-23 DP83TG720 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
W0C	W 0C	Write 0 to clear
W0S	W 0S	Write 0 to set
WMC	W	Write
WMC,0	W	Write
WMC,1	W	Write
WSC	W	Write
WSC,0	W	Write
Reset or Default Value
-n		Value after reset or the default value

7.6.2.1 BMCR Register (Offset = 0h) [Reset = 0140h]

BMCR is shown in Figure 7-18 and described in Table 7-24.

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Figure 7-18 BMCR Register

15	14	13	12	11	10	9	8
mii_reset	loopback	RESERVED	RESERVED	power_down	isolate	RESERVED	RESERVED
R/WMC-0h	R/W-0h	R-0h	R-0h	R/W-0h	R/W-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED	speed_sel_msb	RESERVED	RESERVED
R-0h	R-1h	R-0h	R-0h

Table 7-24 BMCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	mii_reset	R/WMC	0h	1b = Digital in reset and all MII regs (0x0 - 0xF) reset to default 0b = No reset
14	loopback	R/W	0h	1b = MII loopback 0b = No MII loopback
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	power_down	R/W	0h	1b = Power down via register or pin 0b = Normal mode
10	isolate	R/W	0h	1b = MAC isolate mode (No output to MAC from the PHY) 0b = Normal Mode
9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	speed_sel_msb	R	1h	0b= Reserved 1b= 1000 Mb/s
5	RESERVED	R	0h	Reserved
4-0	RESERVED	R	0h	Reserved

7.6.2.2 BMSR Register (Offset = 1h) [Reset = 0141h]

BMSR is shown in Figure 7-19 and described in Table 7-25.

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Figure 7-19 BMSR Register

15	14	13	12	11	10	9	8
RESERVED	RESERVED	RESERVED	RESERVED	RESERVED	RESERVED	RESERVED	extended_status
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-1h

7	6	5	4	3	2	1	0
unidirectional_ability	preamble_supression	aneg_complete	remote_fault	aneg_ability	link_status	jabber_detect	extended_capability
R-0h	R-1h	R-0h	R/W0C-0h	R-0h	R/W0S-0h	R/W0C-0h	R-1h

Table 7-25 BMSR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	extended_status	R	1h	1b = Extended status information in Register 15 0b = No extended status information in Register 15
7	unidirectional_ability	R	0h	Reserved
6	preamble_supression	R	1h	1b = PHY accepts management frames with preamble suppressed. 0b = PHY does not accept management frames with preamble suppressed
5	aneg_complete	R	0h	Reserved
4	remote_fault	R/W0C	0h	Reserved
3	aneg_ability	R	0h	Reserved
2	link_status	R/W0S	0h	1b = link is up 0b = link down
1	jabber_detect	R/W0C	0h	Reserved
0	extended_capability	R	1h	1b = extended register capabilities 0b = basic register set capabilities only

7.6.2.3 PHYID1 Register (Offset = 2h) [Reset = 2000h]

PHYID1 is shown in Figure 7-20 and described in Table 7-26.

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Figure 7-20 PHYID1 Register

15	14	13	12	11	10	9	8
oui_21_16
R-2000h

7	6	5	4	3	2	1	0
oui_21_16
R-2000h

Table 7-26 PHYID1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	oui_21_16	R	2000h	Unique identifier for the part

7.6.2.4 PHYID2 Register (Offset = 3h) [Reset = A284h]

PHYID2 is shown in Figure 7-21 and described in Table 7-27.

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Figure 7-21 PHYID2 Register

15	14	13	12	11	10	9	8
oui_5_0						model_number
R-28h						R-28h

7	6	5	4	3	2	1	0
model_number				rev_number
R-28h				R-4h

Table 7-27 PHYID2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	oui_5_0	R	28h	Unique identifier for the part
9-4	model_number	R	28h	Unique identifier for the part
3-0	rev_number	R	4h	Unique identifier for the part

7.6.2.5 REGCR Register (Offset = Dh) [Reset = 0000h]

REGCR is shown in Figure 7-22 and described in Table 7-28.

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Figure 7-22 REGCR Register

15	14	13	12	11	10	9	8
Extended Register Command		RESERVED
R/W-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED			DEVAD
R-0h			R/W-0h

Table 7-28 REGCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	Extended Register Command	R/W	0h	00b = Address 01b = Data, no post increment 10b = Data, post increment on read and write 11b = Data, post increment on write only
13-5	RESERVED	R	0h	Reserved
4-0	DEVAD	R/W	0h	MMD field for indirect register access

7.6.2.6 ADDAR Register (Offset = Eh) [Reset = 0000h]

ADDAR is shown in Figure 7-23 and described in Table 7-29.

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Figure 7-23 ADDAR Register

15	14	13	12	11	10	9	8
Address/Data
R/W-0h

7	6	5	4	3	2	1	0
Address/Data
R/W-0h

Table 7-29 ADDAR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Address/Data	R/W	0h	Address Data field for indirect register access

7.6.2.7 MII_REG_10 Register (Offset = 10h) [Reset = 0004h]

MII_REG_10 is shown in Figure 7-24 and described in Table 7-30.

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Figure 7-24 MII_REG_10 Register

15	14	13	12	11	10	9	8
RESERVED					RESERVED	descr_lock_bit	RESERVED
R-0h					R-0h	R/W0S-0h	R-0h

7	6	5	4	3	2	1	0
mii_int_bit	RESERVED			mii_loopback	duplex_mode_env	RESERVED	link_status_bit
R-0h	R-0h			R-0h	R-1h	R-0h	R-0h

Table 7-30 MII_REG_10 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	descr_lock_bit	R/W0S	0h	1b = Descrambler is locked 0b = Descrmabler is unlocked atleast once
8	RESERVED	R	0h	Reserved
7	mii_int_bit	R	0h	1b = Interrupt pin had been set 0b = Interrupts pin not set Cleared on Read
6-4	RESERVED	R	0h	Reserved
3	mii_loopback	R	0h	1b = MII loopback 0b = No MII loopback
2	duplex_mode_env	R	1h	1b = Full duplex 0b = Half duplex
1	RESERVED	R	0h	Reserved
0	link_status_bit	R	0h	1b = link is up 0b = link had been down

7.6.2.8 MII_REG_11 Register (Offset = 11h) [Reset = 000Bh]

MII_REG_11 is shown in Figure 7-25 and described in Table 7-31.

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Figure 7-25 MII_REG_11 Register

15	14	13	12	11	10	9	8
RESERVED	RESERVED	RESERVED		RESERVED	RESERVED	RESERVED	RESERVED
R-0h	R-0h	R-0h		R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED	RESERVED	RESERVED		int_polarity	force_interrupt	int_en	RESERVED
R-0h	R-0h	R-0h		R/W-1h	R/W-0h	R/W-1h	R-0h

Table 7-31 MII_REG_11 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13-12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5-4	RESERVED	R	0h	Reserved
3	int_polarity	R/W	1h	1b = Active low 0b = Active high
2	force_interrupt	R/W	0h	1b = Force interrupt pin 0b = Do not force interrupt pin
1	int_en	R/W	1h	1b = Enable interrupts 0b = Disable interrupts
0	RESERVED	R	0h	Reserved

7.6.2.9 MII_REG_12 Register (Offset = 12h) [Reset = 0000h]

MII_REG_12 is shown in Figure 7-26 and described in Table 7-32.

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Figure 7-26 MII_REG_12 Register

15	14	13	12	11	10	9	8
RESERVED	energy_det_int	link_int	RESERVED	esd_int	ms_train_done_int	RESERVED	RESERVED
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED	energy_det_int_en	link_int_en	RESERVED	esd_int_en	ms_train_done_int_en	RESERVED	RESERVED
R-0h	R/W-0h	R/W-0h	R-0h	R/W-0h	R/W-0h	R-0h	R-0h

Table 7-32 MII_REG_12 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	energy_det_int	R	0h	Energy det change interrupt status
13	link_int	R	0h	Link status change interrupt status
12	RESERVED	R	0h	Reserved
11	esd_int	R	0h	ESD fault detected interrupt status
10	ms_train_done_int	R	0h	Training done interrupt status
9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	energy_det_int_en	R/W	0h	Energy det change interrupt enable
5	link_int_en	R/W	0h	Link status change interrupt enable
4	RESERVED	R	0h	Reserved
3	esd_int_en	R/W	0h	ESD fault detected interrupt enable
2	ms_train_done_int_en	R/W	0h	Training done interrupt enable
1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved

7.6.2.10 MII_REG_13 Register (Offset = 13h) [Reset = 0000h]

MII_REG_13 is shown in Figure 7-27 and described in Table 7-33.

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Figure 7-27 MII_REG_13 Register

15	14	13	12	11	10	9	8
under_volt_int	over_volt_int	RESERVED	RESERVED	over_temp_int	RESERVED	pol_change_int	RESERVED
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
under_volt_int_en	over_volt_int_en	RESERVED	RESERVED	over_temp_int_en	RESERVED	pol_change_int_en	RESERVED
R/W-0h	R/W-0h	R-0h	R-0h	R/W-0h	R-0h	R/W-0h	R-0h

Table 7-33 MII_REG_13 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	under_volt_int	R	0h	Under volt interrupt status
14	over_volt_int	R	0h	Over volt interrupt status
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	over_temp_int	R	0h	Over temp interrupt status
10	RESERVED	R	0h	Reserved
9	pol_change_int	R	0h	Data polarity change interrupt status
8	RESERVED	R	0h	Reserved
7	under_volt_int_en	R/W	0h	Under volt interrupt enable
6	over_volt_int_en	R/W	0h	Over volt interrupt enable
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	over_temp_int_en	R/W	0h	Over temp interrupt enable
2	RESERVED	R	0h	Reserved
1	pol_change_int_en	R/W	0h	Data Polarity change interrupt enable
0	RESERVED	R	0h	Reserved

7.6.2.11 MII_REG_16 Register (Offset = 16h) [Reset = 0000h]

MII_REG_16 is shown in Figure 7-28 and described in Table 7-34.

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Figure 7-28 MII_REG_16 Register

15	14	13	12	11	10	9	8
RESERVED					RESERVED	RESERVED	core_pwr_mode
R-0h					R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED	loopback_mode
R-0h	R/W-0h

Table 7-34 MII_REG_16 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	core_pwr_mode	R	0h	1b = Core is is normal power mode 0b = Core is in power down or sleep mode
7	RESERVED	R	0h	Reserved
6-0	loopback_mode	R/W	0h	000001b = PCS loop 000010b = RS loop 000100b = Digital loop 001000B = Analog loop 010000b = Reverse loop

7.6.2.12 MII_REG_18 Register (Offset = 18h) [Reset = 0008h]

MII_REG_18 is shown in Figure 7-29 and described in Table 7-35.

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Figure 7-29 MII_REG_18 Register

15	14	13	12	11	10	9	8
ack_received_int	tx_valid_clr_int	RESERVED	RESERVED	por_done_int	RESERVED	RESERVED	RESERVED
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
ack_received_int_en	tx_valid_clr_int_en	RESERVED	RESERVED	por_done_int_en	RESERVED	RESERVED	RESERVED
R/W-0h	R/W-0h	R-0h	R-0h	R/W-1h	R-0h	R-0h	R-0h

Table 7-35 MII_REG_18 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	ack_received_int	R	0h	Ack received interrupt status (OAM)
14	tx_valid_clr_int	R	0h	mr_tx_valid clear interrupt status (OAM)
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	por_done_int	R	0h	POR done interrupt status
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7	ack_received_int_en	R/W	0h	Ack received interrupt enable (OAM)
6	tx_valid_clr_int_en	R/W	0h	mr_tx_valid clear interrupt enable (OAM)
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	por_done_int_en	R/W	1h	POR done interrupt enable
2	RESERVED	R	0h	Reserved
1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved

7.6.2.13 MII_REG_19 Register (Offset = 19h) [Reset = 00XXh]

MII_REG_19 is shown in Figure 7-30 and described in Table 7-36.

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Figure 7-30 MII_REG_19 Register

15	14	13	12	11	10	9	8
RESERVED					RESERVED	RESERVED
R-0h					R-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED			SOR_PHYADDR
R-0h			R-Xh

Table 7-36 MII_REG_19 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9-5	RESERVED	R	0h	Reserved
4-0	SOR_PHYADDR	R	X	PHY ADDRESS latched from strap

7.6.2.14 MII_REG_1E Register (Offset = 1Eh) [Reset = 0000h]

MII_REG_1E is shown in Figure 7-31 and described in Table 7-37.

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Figure 7-31 MII_REG_1E Register

15	14	13	12	11	10	9	8
tdr_start	cfg_tdr_auto_run	RESERVED
R/WMC-0h	R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED						tdr_done	tdr_fail
R-0h						R-0h	R-0h

Table 7-37 MII_REG_1E Register Field Descriptions

Bit	Field	Type	Reset	Description
15	tdr_start	R/WMC	0h	1b = TDR start Bit is cleared after TDR run is complete
14	cfg_tdr_auto_run	R/W	0h	1b = TDR start automatically on link down 0b = TDR start manually using 0x1E[15]
13-2	RESERVED	R	0h	Reserved
1	tdr_done	R	0h	TDR done status 1b = TDR done 0b = TDR on-going or not initiated
0	tdr_fail	R	0h	When tdr_done status is 1, this bit inidicates if TDR ran successfully 1b = TDR run failed 0b = TDR ran successfully

7.6.2.15 MII_REG_1F Register (Offset = 1Fh) [Reset = 0000h]

MII_REG_1F is shown in Figure 7-32 and described in Table 7-38.

Return to the Summary Table.

Figure 7-32 MII_REG_1F Register

15	14	13	12	11	10	9	8
sw_global_reset	digital_reset	RESERVED	RESERVED
R/WMC-0h	R/WMC-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED	RESERVED	RESERVED	RESERVED
R-0h	R-0h	R-0h	R-0h

Table 7-38 MII_REG_1F Register Field Descriptions

Bit	Field	Type	Reset	Description
15	sw_global_reset	R/WMC	0h	Hardware reset - Reset digital + register file This bit is self clearing
14	digital_reset	R/WMC	0h	Soft reset - Reset only digital core This bit is self clearing
13	RESERVED	R	0h	Reserved
12-8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4-0	RESERVED	R	0h	Reserved

7.6.2.16 LSR Register (Offset = 180h) [Reset = 0000h]

LSR is shown in Figure 7-33 and described in Table 7-39.

Return to the Summary Table.

Figure 7-33 LSR Register

15	14	13	12	11	10	9	8
link_up	link_down	phy_ctrl_send_data	link_status	RESERVED
R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED	RESERVED	RESERVED	RESERVED	channel_ok	descr_sync	loc_rcvr_status	rem_rcvr_status
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 7-39 LSR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	link_up	R	0h	Link up as defined by CnS
14	link_down	R	0h	Link down as defined by CnS
13	phy_ctrl_send_data	R	0h	Phy control in send data status
12	link_status	R	0h	IEEE defined Live Link status
11-8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	channel_ok	R	0h	channel okay status
2	descr_sync	R	0h	Descrambler lock status
1	loc_rcvr_status	R	0h	Local receiver status
0	rem_rcvr_status	R	0h	Remote receiver status

7.6.2.17 LPS_CFG2 Register (Offset = 18Bh) [Reset = 0000h]

LPS_CFG2 is shown in Figure 7-34 and described in Table 7-40.

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Figure 7-34 LPS_CFG2 Register

15	14	13	12	11	10	9	8
RESERVED							ed_en
R-0h							R/W-0h

7	6	5	4	3	2	1	0
sleep_en	cfg_auto_mode_en_strap	RESERVED	RESERVED	RESERVED	RESERVED	RESERVED	RESERVED
R/W-0h	R/WMC,1-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 7-40 LPS_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R	0h	Reserved
8	ed_en	R/W	0h	1b = Enable energy detection on MDI 0b = Disable energy detection on MDI
7	sleep_en	R/W	0h	1b = Allow PHY to enter sleep 0b = Do not allow PHY to enter sleep
6	cfg_auto_mode_en_strap	R/WMC,1	0h	LPS autonomous mode enable 1b = PHY enters normal mode on power up 0b = PHY enters standby mode on power up
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2	RESERVED	R	0h	Reserved
1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved

7.6.2.18 LPS_CFG3 Register (Offset = 18Ch) [Reset = 0000h]

LPS_CFG3 is shown in Figure 7-35 and described in Table 7-41.

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Figure 7-35 LPS_CFG3 Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED	RESERVED	RESERVED	cfg_lps_pwr_mode_4	RESERVED	RESERVED	RESERVED	cfg_lps_pwr_mode_0
R-0h	R-0h	R-0h	R/WMC,0-0h	R-0h	R-0h	R-0h	R/WMC,0-0h

Table 7-41 LPS_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	cfg_lps_pwr_mode_4	R/WMC,0	0h	Set to enter standby mode
3	RESERVED	R	0h	Reserved
2	RESERVED	R	0h	Reserved
1	RESERVED	R	0h	Reserved
0	cfg_lps_pwr_mode_0	R/WMC,0	0h	Set to enter normal mode

7.6.2.19 LPS_STATUS Register (Offset = 18Eh) [Reset = 0000h]

LPS_STATUS is shown in Figure 7-36 and described in Table 7-42.

Return to the Summary Table.

Figure 7-36 LPS_STATUS Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED	status_lps_st
R-0h	R-0h

Table 7-42 LPS_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-7	RESERVED	R	0h	Reserved
6-0	status_lps_st	R	0h	Observe LPS state : 0x2 = Standby mode 0x4 = Normal mode

7.6.2.20 TDR_TC12 Register (Offset = 30Fh) [Reset = 0000h]

TDR_TC12 is shown in Figure 7-37 and described in Table 7-43.

Return to the Summary Table.

Figure 7-37 TDR_TC12 Register

15	14	13	12	11	10	9	8
RESERVED		fault_loc
R-0h		R-0h

7	6	5	4	3	2	1	0
tdr_state				RESERVED		tdr_activation
R-0h				R-0h		R-0h

Table 7-43 TDR_TC12 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0h	Reserved
13-8	fault_loc	R	0h	See TC12
7-4	tdr_state	R	0h	See TC12
3-2	RESERVED	R	0h	Reserved
1-0	tdr_activation	R	0h	See TC12

7.6.2.21 A2D_REG_05 Register (Offset = 405h) [Reset = 6400h]

A2D_REG_05 is shown in Figure 7-38 and described in Table 7-44.

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Figure 7-38 A2D_REG_05 Register

15	14	13	12	11	10	9	8
ld_bias_1p0v_sl						RESERVED
R/W-19h						R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 7-44 A2D_REG_05 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	ld_bias_1p0v_sl	R/W	19h	Bits to control the DAC current of LD and hence the swing. 001010b = 400mV 001011b = 440mV 001100b = 480mV 001101b = 520mV 001110b = 560mV 001111b = 600mV 010000b = 640mV 010001b = 680mV 010010b = 720mV 010011b = 760mV 010100b = 800mV 010101b = 840mV 010110b = 880mV 010111b = 920mV 011000b = 960mV 011001b = 1000mV 011010b = 1040mV 011011b = 1080mV 011100b = 1120mV 011101b = 1160mV 011110b = 1200mV
9-0	RESERVED	R	0h	Reserved

7.6.2.22 A2D_REG_30 Register (Offset = 41Eh) [Reset = 0000h]

A2D_REG_30 is shown in Figure 7-39 and described in Table 7-45.

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Figure 7-39 A2D_REG_30 Register

15	14	13	12	11	10	9	8
RESERVED							spare_in_2_fromdig_sl_force_en
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED	RESERVED	RESERVED	RESERVED	RESERVED
R-0h	R-0h	R-0h	R-0h	R-0h

Table 7-45 A2D_REG_30 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R	0h	Reserved
8	spare_in_2_fromdig_sl_force_en	R/W	0h	Force control enable for Reg0x042F
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3-0	RESERVED	R	0h	Reserved

7.6.2.23 A2D_REG_40 Register (Offset = 428h) [Reset = 6002h]

A2D_REG_40 is shown in Figure 7-40 and described in Table 7-46.

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Figure 7-40 A2D_REG_40 Register

15	14	13	12	11	10	9	8
RESERVED	SGMII_TESTMODE		RESERVED	SGMII_SOP_SON_SLEW_CTRL	RESERVED	RESERVED
R-0h	R/W-3h		R-0h	R/W-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED	RESERVED						RESERVED
R-0h	R-0h						R-0h

Table 7-46 A2D_REG_40 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14-13	SGMII_TESTMODE	R/W	3h	00b = 1000mV Sgmii output swing 01b = 1260mV Sgmii output swing 10b = 900mV Sgmii output swing 11b = 720mV Sgmii output swing
12	RESERVED	R	0h	Reserved
11	SGMII_SOP_SON_SLEW_CTRL	R/W	0h	0b =Default output rise/fall time 1b = Slow output rise/fall time
10	RESERVED	R	0h	Reserved
9-8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6-1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved

7.6.2.24 A2D_REG_41 Register (Offset = 429h) [Reset = 0030h]

A2D_REG_41 is shown in Figure 7-41 and described in Table 7-47.

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Figure 7-41 A2D_REG_41 Register

15	14	13	12	11	10	9	8
RESERVED					RESERVED	RESERVED	RESERVED
R-0h					R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED						SGMII_IO_LOOPBACK_EN	RESERVED
R-0h						R/W-0h	R-0h

Table 7-47 A2D_REG_41 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7-2	RESERVED	R	0h	Reserved
1	SGMII_IO_LOOPBACK_EN	R/W	0h	1b = Connects RX and TX signals internally to provide internal loopback option without external components.
0	RESERVED	R	0h	Reserved

7.6.2.25 A2D_REG_44 Register (Offset = 42Ch) [Reset = 0000h]

A2D_REG_44 is shown in Figure 7-42 and described in Table 7-48.

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Figure 7-42 A2D_REG_44 Register

15	14	13	12	11	10	9	8
RESERVED	RESERVED	RESERVED	RESERVED	RESERVED	RESERVED	RESERVED	RESERVED
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED	RESERVED	RESERVED	SGMII_DIG_LOOPBACK_EN	RESERVED			RESERVED
R-0h	R-0h	R-0h	R/W-0h	R-0h			R-0h

Table 7-48 A2D_REG_44 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	SGMII_DIG_LOOPBACK_EN	R/W	0h	1b = Loops back TX data to RX before the IO
3-1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved

7.6.2.26 A2D_REG_47 Register (Offset = 42Fh) [Reset = 0000h]

A2D_REG_47 is shown in Figure 7-43 and described in Table 7-49.

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Figure 7-43 A2D_REG_47 Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				RESERVED	spare_in_2_fromdig_sl_2	spare_in_2_fromdig_sl_1	spare_in_2_fromdig_sl_0
R-0h				R-0h	R/W-0h	R/W-0h	R/W-0h

Table 7-49 A2D_REG_47 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2	spare_in_2_fromdig_sl_2	R/W	0h	energy lost indication force control value
1	spare_in_2_fromdig_sl_1	R/W	0h	energy lost detector enable force control value
0	spare_in_2_fromdig_sl_0	R/W	0h	[0] - sleep enable force control value Force control enable is controlled by reg0x041E[8]

7.6.2.27 A2D_REG_48 Register (Offset = 430h) [Reset = 0960h]

A2D_REG_48 is shown in Figure 7-44 and described in Table 7-50.

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Figure 7-44 A2D_REG_48 Register

15	14	13	12	11	10	9	8
RESERVED	RESERVED	RESERVED	RESERVED	DLL_TX_DELAY_CTRL_SL
R-0h	R-0h	R-0h	R-0h	R/W-9h

7	6	5	4	3	2	1	0
DLL_RX_DELAY_CTRL_SL				RESERVED
R/W-6h				R-0h

Table 7-50 A2D_REG_48 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11-8	DLL_TX_DELAY_CTRL_SL	R/W	9h	Refer to electrical specification for delay vs code information.
7-4	DLL_RX_DELAY_CTRL_SL	R/W	6h	Refer to electrical specification for delay vs code information.
3-0	RESERVED	R	0h	Reserved

7.6.2.28 A2D_REG_66 Register (Offset = 442h) [Reset = 0000h]

A2D_REG_66 is shown in Figure 7-45 and described in Table 7-51.

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Figure 7-45 A2D_REG_66 Register

15	14	13	12	11	10	9	8
RESERVED	esd_event_count						RESERVED
R-0h	R-0h						R-0h

7	6	5	4	3	2	1	0
RESERVED			RESERVED	RESERVED
R-0h			R-0h	R-0h

Table 7-51 A2D_REG_66 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14-9	esd_event_count	R	0h	Number gives the number of esd events on the copper channel
8	RESERVED	R	0h	Reserved
7-5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3-0	RESERVED	R	0h	Reserved

7.6.2.29 LEDS_CFG_1 Register (Offset = 450h) [Reset = 2610h]

LEDS_CFG_1 is shown in Figure 7-46 and described in Table 7-52.

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Figure 7-46 LEDS_CFG_1 Register

15	14	13	12	11	10	9	8
RESERVED	leds_bypass_stretching	leds_blink_rate		led_2_option
R-0h	R/W-0h	R/W-2h		R/W-6h

7	6	5	4	3	2	1	0
led_1_option				led_0_option
R/W-1h				R/W-0h

Table 7-52 LEDS_CFG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	leds_bypass_stretching	R/W	0h	Bypass LED Signal Stretch
13-12	leds_blink_rate	R/W	2h	Blink Rate for the LED - 00b = 20Hz (50mSec) 01b = 10Hz (100mSec) 10b = 5Hz (200mSec) 11b = 2Hz (500mSec)
11-8	led_2_option	R/W	6h	0000b = link OK 0001b = link OK + blink on TX/RX activity 0010b = link OK + blink on TX activity 0011b = link OK + blink on RX activity 0100b = link OK + 100Base-T1 Master 0101b = link OK + 100Base-T1 Slave 0110b = TX/RX activity with stretch option 0111b = Reserved 1000b = Reserved 1001b = Link lost (remains on until register 0x1 is read) 1010b = PRBS error latch until cleared by 0x620(1) 1011b = XMII TX/RX Error with stretch option
7-4	led_1_option	R/W	1h	0000b = link OK 0001b = link OK + blink on TX/RX activity 0010b = link OK + blink on TX activity 0011b = link OK + blink on RX activity 0100b = link OK + 100Base-T1 Master 0101b = link OK + 100Base-T1 Slave 0110b = TX/RX activity with stretch option 0111b = Reserved 1000b = Reserved 1001b = Link lost (remains on until register 0x1 is read) 1010b = PRBS error (latch until cleared by 0x620(1) 1011b = XMII TX/RX Error with stretch option
3-0	led_0_option	R/W	0h	0000b = link OK 0001b = link OK + blink on TX/RX activity 0010b = link OK + blink on TX activity 0011b = link OK + blink on RX activity 0100b = link OK + 100Base-T1 Master 0101b = link OK + 100Base-T1 Slave 0110b = TX/RX activity with stretch option 0111b = Reserved 1000b = Reserved 1001b = Link lost (remains on until register 0x1 is read) 1010b = PRBS error (latch until cleared by 0x620(1) 1011b = XMII TX/RX Error with stretch option

7.6.2.30 LEDS_CFG_2 Register (Offset = 451h) [Reset = 0000h]

LEDS_CFG_2 is shown in Figure 7-47 and described in Table 7-53.

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Figure 7-47 LEDS_CFG_2 Register

15	14	13	12	11	10	9	8
RESERVED		RESERVED				XXXX	RESERVED
R-0h		R-0h					R-0h

7	6	5	4	3	2	1	0
RESERVED	RESERVED	RESERVED	RESERVED	led_1_polarity	RESERVED	RESERVED	led_0_polarity
R-0h	R-0h	R-0h	R-0h	R/W-0h	R-0h	R-0h	R/W-0h

Table 7-53 LEDS_CFG_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0h	Reserved
13-10	RESERVED	R	0h	Reserved
11-9	cfg_ieee_compl_sel	R/W	0h	Observe IEEE Compliance signals in LED_0_GPIO_0, when LED_0_GPIO_CTRL= 'h5 as follows - 000b = loc_rcvr_status 001b = rem_rcvr_status 010b = loc_snr_margin 011b = rem_phy_ready 100b = pma_watchdog_status 101b = link_sync_link_control
8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	led_1_polarity	R/W	0h	LED_1 polarity
2	RESERVED	R	0h	Reserved
1	RESERVED	R	0h	Reserved
0	led_0_polarity	R/W	0h	LED_0 polarity

7.6.2.31 IO_MUX_CFG_1 Register (Offset = 452h) [Reset = 0000h]

IO_MUX_CFG_1 is shown in Figure 7-48 and described in Table 7-54.

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Figure 7-48 IO_MUX_CFG_1 Register

15	14	13	12	11	10	9	8
RESERVED		RESERVED			led_1_gpio_ctrl
R-0h		R-0h			R/W-0h

7	6	5	4	3	2	1	0
RESERVED		RESERVED			led_0_gpio_ctrl
R-0h		R-0h			R/W-0h

Table 7-54 IO_MUX_CFG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0h	Reserved
13-11	RESERVED	R	0h	Reserved
10-8	led_1_gpio_ctrl	R/W	0h	Controls the output of LED_1 IO - 000b = LED_1 (default: link OK + blink on TX/RX activity) 001b = Reserved 010b = RGMII data match indication 011b = Under-Voltage indication 100b = Interrupt 101b = IEEE compliance signals 110b = constant 0 111b = constant 1
7-6	RESERVED	R	0h	Reserved
5-3	RESERVED	R	0h	Reserved
2-0	led_0_gpio_ctrl	R/W	0h	Controls the output of LED_0 IO: 000b = LED_0 (default: LINK) 001b = Reserved 010b = RGMII data match indication 011b = Under-Voltage indication 100b = Interrupt 101b = IEEE compliance signals (see 0x451[11:9]) 110b = constant 0 111b = constant 1

7.6.2.32 IO_MUX_CFG_2 Register (Offset = 453h) [Reset = 0001h]

IO_MUX_CFG_2 is shown in Figure 7-49 and described in Table 7-55.

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Figure 7-49 IO_MUX_CFG_2 Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED		clk_o_clk_source			clk_o_gpio_ctrl
R-0h		R/W-0h			R/W-1h

Table 7-55 IO_MUX_CFG_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-6	RESERVED	R	0h	Reserved
5-3	clk_o_clk_source	R/W	0h	Clock Observable in CLK_O pin - 000b = xi_osc_25m_1p0v_dl (25MHz crystal output - from analog) 001b = Reserved 010b = Reserved 011b = 125MHz clock 100b = 125MHz clock 101b = Reserved 110b = Reserved 111b = Reserved
2-0	clk_o_gpio_ctrl	R/W	1h	Controls the output of CLK_O IO - 000b = LED_2 (default: TX/RX activity with stretch option(LED_2_OPTION=0x6) 001b = Clock out (see 0x453[5:3]) 010b = RGMII data match indication 011b = Under-Voltage indication 100b = constant 0 101b = constant 0 110b = constant 0 111b = constant 1

7.6.2.33 IO_CONTROL_3 Register (Offset = 456h) [Reset = 0108h]

IO_CONTROL_3 is shown in Figure 7-50 and described in Table 7-56.

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Figure 7-50 IO_CONTROL_3 Register

15	14	13	12	11	10	9	8
RESERVED						cfg_mac_rx_impedance
R-0h						R/W-8h

7	6	5	4	3	2	1	0
cfg_mac_rx_impedance			RESERVED
R/W-8h			R-0h

Table 7-56 IO_CONTROL_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-5	cfg_mac_rx_impedance	R/W	8h	Slew Rate Control for RGMII pads - 01010b = Medium Slew (OA tr/tf compliant, max tr/tf = 1ns) 01011b = Slowest Slew (For low emissions, max tr/tf = 1.2ns) 01000b = Default mode (rgmii tr/tf compliant, max tr/tf=750ps)
4-0	RESERVED	R	0h	Reserved

7.6.2.34 SOR_VECTOR_1 Register (Offset = 45Dh) [Reset = 0000h]

SOR_VECTOR_1 is shown in Figure 7-51 and described in Table 7-57.

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Strap Status Register:
This register has information on modes selected based on straps. Any override of mode using other registers will not be reflected in this register

Figure 7-51 SOR_VECTOR_1 Register

15	14	13	12	11	10	9	8
RGMII_TX_SHIFT	RGMII_RX_SHIFT	SGMII_EN	RGMII_EN	RESERVED			MAC_MODE
R-0h	R-0h	R-0h	R-0h	R-0h			R-0h

7	6	5	4	3	2	1	0
MAC_MODE		MAS/SLV	PHY_AD
R-0h		R-0h	R-0h

Table 7-57 SOR_VECTOR_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RGMII_TX_SHIFT	R	0h	0x0 = TX shift disbaled 0x1 = TX shift enabled
14	RGMII_RX_SHIFT	R	0h	0x0 = RX shift disabled 0x1 = RX shift enabled
13	SGMII_EN	R	0h	0x0 = SGMII disabled 0x1 = SGMII enabled
12	RGMII_EN	R	0h	0x0 = RGMII disabled 0x1 = RGMII enabled
11-9	RESERVED	R	0h	Reserved
8-6	MAC_MODE	R	0h	0x0 = SGMII 0x1 = Reserved 0x2 = Reserved 0x3 = Reserved 0x4 = RGMII align 0x5 = RGMII TX shift 0x6 = RGMII TX and RX shift 0x7 = RGMII RX shift
5	MAS/SLV	R	0h	0x0 = Slave 0x1 = Master
4-0	PHY_AD	R	0h	0x0 = PHY address 0 0x4 = PHY address 4 0x5 = PHY address 5 0x8 = PHY address 8 0xA = PHY address A 0xC = PHY address C 0xD = PHY address D 0xE = PHY address E 0xF = PHY address F

7.6.2.35 SOR_VECTOR_2 Register (Offset = 45Eh) [Reset = 0000h]

SOR_VECTOR_2 is shown in Figure 7-52 and described in Table 7-58.

Return to the Summary Table.

Strap Status Register:
This register has information on modes selected based on straps. Any override of mode using other registers will not be reflected in this register

Figure 7-52 SOR_VECTOR_2 Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							AUTO/MANAGED
R-0h							R-0h

Table 7-58 SOR_VECTOR_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-1	RESERVED	R	0h	Reserved
0	AUTO/MANAGED	R	0h	0x0 = Autonomous mode enabled 0x1 = Managed mode enabled

7.6.2.36 MONITOR_CTRL2 Register (Offset = 468h) [Reset = 0920h]

MONITOR_CTRL2 is shown in Figure 7-53 and described in Table 7-59.

Return to the Summary Table.

Figure 7-53 MONITOR_CTRL2 Register

15	14	13	12	11	10	9	8
RESERVED	cfg_rd_data			RESERVED			RESERVED
R-0h	R/W-0h			R-0h			R-0h

7	6	5	4	3	2	1	0
RESERVED		RESERVED			RESERVED
R-0h		R-0h			R-0h

Table 7-59 MONITOR_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14-12	cfg_rd_data	R/W	0h	Sensor select for read-out: 001b = VDDA 010b = VDD1P0 011b = VDDIO 100b = Temperature
11-9	RESERVED	R	0h	Reserved
8-6	RESERVED	R	0h	Reserved
5-3	RESERVED	R	0h	Reserved
2-0	RESERVED	R	0h	Reserved

7.6.2.37 MONITOR_CTRL4 Register (Offset = 46Ah) [Reset = 0094h]

MONITOR_CTRL4 is shown in Figure 7-54 and described in Table 7-60.

Return to the Summary Table.

Figure 7-54 MONITOR_CTRL4 Register

15	14	13	12	11	10	9	8
RESERVED							RESERVED
R-0h							R-0h

7	6	5	4	3	2	1	0
RESERVED	RESERVED	RESERVED		RESERVED	cfg_reset	periodic	start
R-0h	R-0h	R-0h		R-0h	R/W-1h	R/W-0h	R/WSC-0h

Table 7-60 MONITOR_CTRL4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5-4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2	cfg_reset	R/W	1h	0b = Enable the monitor 1b = Monitor is held in reset state At any point of time, if the signal is changed to 1, the module abruptly goes to reset state
1	periodic	R/W	0h	0b = Monitor is enabled only when start is set for one iteration 1b = Monitor is enabled for periodic iteration
0	start	R/WSC	0h	Start indication for sensor monitor FSM, self clearing

7.6.2.38 MONITOR_STAT1 Register (Offset = 47Bh) [Reset = 0000h]

MONITOR_STAT1 is shown in Figure 7-55 and described in Table 7-61.

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Figure 7-55 MONITOR_STAT1 Register

15	14	13	12	11	10	9	8
stat_rd_data
R-0h

7	6	5	4	3	2	1	0
stat_rd_data
R-0h

Table 7-61 MONITOR_STAT1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	stat_rd_data	R	0h	Read sensor data

7.6.2.39 RS_DECODER Register (Offset = 510h) [Reset = 2D50h]

RS_DECODER is shown in Figure 7-56 and described in Table 7-62.

Return to the Summary Table.

Figure 7-56 RS_DECODER Register

15	14	13	12	11	10	9	8
cfg_rs_decoder_bypass	RESERVED	RESERVED
R/W-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED							RESERVED
R-0h							R-0h

Table 7-62 RS_DECODER Register Field Descriptions

Bit	Field	Type	Reset	Description
15	cfg_rs_decoder_bypass	R/W	0h	Bypass RS decoder 0h = RS decoder in use 1h = Bypass RS decoder
14	RESERVED	R	0h	Reserved
13-8	RESERVED	R	0h	Reserved
7-1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved

7.6.2.40 TRAINING_RX_STATUS_7 Register (Offset = 52Bh) [Reset = 0000h]

TRAINING_RX_STATUS_7 is shown in Figure 7-57 and described in Table 7-63.

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Figure 7-57 TRAINING_RX_STATUS_7 Register

15	14	13	12	11	10	9	8
RESERVED			rx_rvrs_pol	RESERVED
R-0h			R-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED				RESERVED
R-0h				R-0h

Table 7-63 TRAINING_RX_STATUS_7 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0h	Reserved
12	rx_rvrs_pol	R	0h	Received polarity 0h = Polarity decoded from received is not inverted 1h = Polarity decoded from receiver is inverted
11-8	RESERVED	R	0h	Reserved
7-4	RESERVED	R	0h	Reserved
3-0	RESERVED	R	0h	Reserved

7.6.2.41 LINK_QUAL_1 Register (Offset = 543h) [Reset = 0000h]

LINK_QUAL_1 is shown in Figure 7-58 and described in Table 7-64.

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Figure 7-58 LINK_QUAL_1 Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
link_training_time
R-0h

Table 7-64 LINK_QUAL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7-0	link_training_time	R	0h	Link training time in ms (TC12)

7.6.2.42 LINK_QUAL_2 Register (Offset = 544h) [Reset = 0000h]

LINK_QUAL_2 is shown in Figure 7-59 and described in Table 7-65.

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Figure 7-59 LINK_QUAL_2 Register

15	14	13	12	11	10	9	8
remote_receiver_time
R-0h

7	6	5	4	3	2	1	0
local_receiver_time
R-0h

Table 7-65 LINK_QUAL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	remote_receiver_time	R	0h	Remote receiver time in ms (TC12)
7-0	local_receiver_time	R	0h	Local receiver time in ms (TC12)

7.6.2.43 LINK_DOWN_LATCH_STAT Register (Offset = 545h) [Reset = 0000h]

LINK_DOWN_LATCH_STAT is shown in Figure 7-60 and described in Table 7-66.

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Figure 7-60 LINK_DOWN_LATCH_STAT Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED		channel_ok_ll	link_fail_inhibit_lh	send_s_sigdet_lh	hi_rfer_lh	block_lock_ll	pma_watchdog_ll
R-0h		R/W0C-0h	R/W0C-0h	R/W0C-0h	R/W0C-0h	R/W0S-0h	R/W0S-0h

Table 7-66 LINK_DOWN_LATCH_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-6	RESERVED	R	0h	Reserved
5	channel_ok_ll	R/W0C	0h	1b = Channel ok was never de-asserted 0b = Channel ok was de-asserted
4	link_fail_inhibit_lh	R/W0C	0h	1b = Link fail inhibit assertion was reported 0b = Link fail inhibit assertion was never reported
3	send_s_sigdet_lh	R/W0C	0h	1b = Send s sigdet assertion was reported 0b = Send s sigdet assertion was never reported
2	hi_rfer_lh	R/W0C	0h	1b = High ri rfer assertion was reported 0b = High ri rfer assertion was never reported
1	block_lock_ll	R/W0S	0h	1b = Block lock de-assertion was never reported 0b = Block lock de-assertion was never reported
0	pma_watchdog_ll	R/W0S	0h	1b = Low pma watchdog was never reported 0b = Low pma watchdof was reported

7.6.2.44 LINK_QUAL_3 Register (Offset = 547h) [Reset = 0000h]

LINK_QUAL_3 is shown in Figure 7-61 and described in Table 7-67.

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Figure 7-61 LINK_QUAL_3 Register

15	14	13	12	11	10	9	8
link_loss_cnt						link_fail_cnt
R-0h						R-0h

7	6	5	4	3	2	1	0
link_fail_cnt
R-0h

Table 7-67 LINK_QUAL_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	link_loss_cnt	R	0h	Link loss count since last power cycle (TC12)
9-0	link_fail_cnt	R	0h	Link fail without link loss count since last power cycle (TC12)

7.6.2.45 LINK_QUAL_4 Register (Offset = 548h) [Reset = 0000h]

LINK_QUAL_4 is shown in Figure 7-62 and described in Table 7-68.

Return to the Summary Table.

Figure 7-62 LINK_QUAL_4 Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							comm_ready
R-0h							R-0h

Table 7-68 LINK_QUAL_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-1	RESERVED	R	0h	Reserved
0	comm_ready	R	0h	Communication ready status (TC12)

7.6.2.46 RS_DECODER_FRAME_STAT_2 Register (Offset = 552h) [Reset = 0000h]

RS_DECODER_FRAME_STAT_2 is shown in Figure 7-63 and described in Table 7-69.

Return to the Summary Table.

Figure 7-63 RS_DECODER_FRAME_STAT_2 Register

15	14	13	12	11	10	9	8
rs_dec_uncorr_frame_cnt
R-0h

7	6	5	4	3	2	1	0
rs_dec_uncorr_frame_cnt
R-0h

Table 7-69 RS_DECODER_FRAME_STAT_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	rs_dec_uncorr_frame_cnt	R	0h	No of uncorrectable RS frames received at RS decoder, clear on read, saturates

7.6.2.47 RS_DECODER_FRAME_STAT_3 Register (Offset = 553h) [Reset = 0000h]

RS_DECODER_FRAME_STAT_3 is shown in Figure 7-64 and described in Table 7-70.

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Figure 7-64 RS_DECODER_FRAME_STAT_3 Register

15	14	13	12	11	10	9	8
rs_dec_err_frame_cnt
R-0h

7	6	5	4	3	2	1	0
rs_dec_err_frame_cnt
R-0h

Table 7-70 RS_DECODER_FRAME_STAT_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	rs_dec_err_frame_cnt	R	0h	No of erroreous RS frames received at RS decoder, clear on read, saturates

7.6.2.48 RGMII_CTRL Register (Offset = 600h) [Reset = 0120h]

RGMII_CTRL is shown in Figure 7-65 and described in Table 7-71.

Return to the Summary Table.

Figure 7-65 RGMII_CTRL Register

15	14	13	12	11	10	9	8
RESERVED						rgmii_rx_half_full_th
R-0h						R/W-2h

7	6	5	4	3	2	1	0
rgmii_rx_half_full_th	rgmii_tx_half_full_th			rgmii_tx_if_en	invert_rgmii_txd	invert_rgmii_rxd	RESERVED
R/W-2h	R/W-2h			R/W-0h	R/W-0h	R/W-0h	R-0h

Table 7-71 RGMII_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-7	rgmii_rx_half_full_th	R/W	2h	RGMII RX sync FIFO half full threshold
6-4	rgmii_tx_half_full_th	R/W	2h	RGMII TX sync FIFO half full threshold
3	rgmii_tx_if_en	R/W	0h	RGMII enable bit Default from strap 0h = RGMII disable 1h = RGMII enable
2	invert_rgmii_txd	R/W	0h	Invert RGMII Tx wire order - full swap [3:0] to [0:3] 0h = Keep RGMII Tx wire order same 1h = Invert RGMII Tx wire order
1	invert_rgmii_rxd	R/W	0h	Invert RGMII Rx wire order - full swap [3:0] to [0:3] 0h = Keep RGMII Rx wire order same 1h = Invert RGMII Rx wire order
0	RESERVED	R	0h	Reserved

7.6.2.49 RGMII_FIFO_STATUS Register (Offset = 601h) [Reset = 0000h]

RGMII_FIFO_STATUS is shown in Figure 7-66 and described in Table 7-72.

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Figure 7-66 RGMII_FIFO_STATUS Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				rgmii_rx_af_full_err	rgmii_rx_af_empty_err	rgmii_tx_af_full_err	rgmii_tx_af_empty_err
R-0h				R/W0C-0h	R/W0C-0h	R/W0C-0h	R/W0C-0h

Table 7-72 RGMII_FIFO_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-4	RESERVED	R	0h	Reserved
3	rgmii_rx_af_full_err	R/W0C	0h	RGMII RX fifo full error 0h = No empty fifo error 1h = RGMII TX full error has been indicated
2	rgmii_rx_af_empty_err	R/W0C	0h	RGMII RX fifo empty error 0h = No empty fifo error 1h = RGMII RX empty error has been indicated
1	rgmii_tx_af_full_err	R/W0C	0h	RGMII TX fifo full error 0h = No empty fifo error 1h = RGMII TX full error has been indicated
0	rgmii_tx_af_empty_err	R/W0C	0h	RGMII TX fifo empty error 0h = No empty fifo error 1h = RGMII TX empty error has been indicated

7.6.2.50 RGMII_DELAY_CTRL Register (Offset = 602h) [Reset = 0000h]

RGMII_DELAY_CTRL is shown in Figure 7-67 and described in Table 7-73.

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Figure 7-67 RGMII_DELAY_CTRL Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						rx_clk_sel	tx_clk_sel
R-0h						R/W-0h	R/W-0h

Table 7-73 RGMII_DELAY_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-2	RESERVED	R	0h	Reserved
1	rx_clk_sel	R/W	0h	In RGMII mode, Enable or disable the internal delay for RXD wrt RX_CLK (use this mode when RGMII_RX_CLK and RGMII_RXD are aligned). The delay magnitude can be configured by programming register 0x430[7:4] 0h = clock and data are aligned 1h = clock is delayed relative to RGMII_RX data
0	tx_clk_sel	R/W	0h	In RGMII mode, Enable or disable the internal delay for TXD wrt TX_CLK (use this mode when RGMII_TX_CLK and RGMII_TXD are aligned). The delay magnitude can be configured by programming register 0x430[11:8] 0h = clock and data are aligned 1h = clock is internally delayed

7.6.2.51 SGMII_CTRL_1 Register (Offset = 608h) [Reset = 007Bh]

SGMII_CTRL_1 is shown in Figure 7-68 and described in Table 7-74.

Return to the Summary Table.

SGMII Register: Available only on DP83TG720S-Q1

Figure 7-68 SGMII_CTRL_1 Register

15	14	13	12	11	10	9	8
sgmii_tx_err_dis	cfg_align_idx_force	cfg_align_idx_value				cfg_sgmii_en	cfg_sgmii_rx_pol_invert
R/W-0h	R/W-0h	R/W-0h				R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
cfg_sgmii_tx_pol_invert	RESERVED		RESERVED	RESERVED	sgmii_autoneg_timer		mr_an_enable
R/W-0h	R-0h		R-0h	R-0h	R/W-1h		R/W-1h

Table 7-74 SGMII_CTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	sgmii_tx_err_dis	R/W	0h	1 = Disable SGMII TX Error indication 0 = Enable SGMII TX Error indication
14	cfg_align_idx_force	R/W	0h	Force word boundray index selection
13-10	cfg_align_idx_value	R/W	0h	when cfg_align_idx_force = 1 This value set the iword boundray index
9	cfg_sgmii_en	R/W	0h	SGMII enable bit Default from strap 0h = SGMII disable 1h = SGMII enable
8	cfg_sgmii_rx_pol_invert	R/W	0h	SGMII RX bus invert polarity 0h = Polarity not inverted 1h = SGMII RX bus invert polarity
7	cfg_sgmii_tx_pol_invert	R/W	0h	SGMII TX bus invert polarity 0h = Polarity not inverted 1h = SGMII TX bus invert polarity
6-5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2-1	sgmii_autoneg_timer	R/W	1h	Selects duration of SGMII Auto-Negotiation timer: 00: 1.6ms 01: 2us 10: 800us 11: 11ms
0	mr_an_enable	R/W	1h	1 = Enable SGMII Auto-Negotaition 0 = Disable SGMII Auto-Negotiation

7.6.2.52 SGMII_STATUS Register (Offset = 60Ah) [Reset = 0000h]

SGMII_STATUS is shown in Figure 7-69 and described in Table 7-75.

Return to the Summary Table.

SGMII Register: Available only on DP83TG720S-Q1

Figure 7-69 SGMII_STATUS Register

15	14	13	12	11	10	9	8
RESERVED			sgmii_page_received	link_status_1000bx	mr_an_complete	cfg_align_en	cfg_sync_status
R-0h			R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
cfg_align_idx				cfg_state
R-0h				R-0h

Table 7-75 SGMII_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0h	Reserved
12	sgmii_page_received	R	0h	Indicates that a new auto neg page was received 0h = No new auto neg page received 1h = A new auto neg page received
11	link_status_1000bx	R	0h	sgmii link status 0h = SGMII link down 1h = SGMII link up
10	mr_an_complete	R	0h	sgmii autoneg complete indication 0h = SGMII autoneg not completed 1h = SGMII autoneg completed
9	cfg_align_en	R	0h	word boundary FSM - align indication
8	cfg_sync_status	R	0h	word boundary FSM - sync status indication 0h = sync not achieved 1h = sync achieved
7-4	cfg_align_idx	R	0h	word boundary index selection
3-0	cfg_state	R	0h	word boundary FSM state

7.6.2.53 SGMII_CTRL_2 Register (Offset = 60Ch) [Reset = 001Bh]

SGMII_CTRL_2 is shown in Figure 7-70 and described in Table 7-76.

Return to the Summary Table.

SGMII Register: Available only on DP83TG720S-Q1

Figure 7-70 SGMII_CTRL_2 Register

15	14	13	12	11	10	9	8
RESERVED							RESERVED
R-0h							R-0h

7	6	5	4	3	2	1	0
RESERVED	mr_restart_an	tx_half_full_th			rx_half_full_th
R-0h	R/WSC,0-0h	R/W-3h			R/W-3h

Table 7-76 SGMII_CTRL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	mr_restart_an	R/WSC,0	0h	Restart sgmii autonegotiation
5-3	tx_half_full_th	R/W	3h	SGMII TX sync FIFO half full threshold
2-0	rx_half_full_th	R/W	3h	SGMII RX sync FIFO half full threshold

7.6.2.54 SGMII_FIFO_STATUS Register (Offset = 60Dh) [Reset = 0000h]

SGMII_FIFO_STATUS is shown in Figure 7-71 and described in Table 7-77.

Return to the Summary Table.

SGMII Register: Available only on DP83TG720S-Q1

Figure 7-71 SGMII_FIFO_STATUS Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				sgmii_rx_af_full_err	sgmii_rx_af_empty_err	sgmii_tx_af_full_err	sgmii_tx_af_empty_err
R-0h				R/W0C-0h	R/W0C-0h	R/W0C-0h	R/W0C-0h

Table 7-77 SGMII_FIFO_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-4	RESERVED	R	0h	Reserved
3	sgmii_rx_af_full_err	R/W0C	0h	SGMII RX fifo full error 0h = No error indication 1h = SGMII RX fifo full error has been indicated
2	sgmii_rx_af_empty_err	R/W0C	0h	SGMII RX fifo empty error 0h = No error indication 1h = SGMII RX fifo empty error has been indicated
1	sgmii_tx_af_full_err	R/W0C	0h	SGMII TX fifo full error 0h = No error indication 1h = SGMII TX fifo full error has been indicated
0	sgmii_tx_af_empty_err	R/W0C	0h	SGMII TX fifo empty error 0h = No error indication 1h = SGMII TX fifo empty error has been indicated

7.6.2.55 PRBS_STATUS_1 Register (Offset = 618h) [Reset = 0000h]

PRBS_STATUS_1 is shown in Figure 7-72 and described in Table 7-78.

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Figure 7-72 PRBS_STATUS_1 Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
prbs_err_ov_cnt
R-0h

Table 7-78 PRBS_STATUS_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7-0	prbs_err_ov_cnt	R	0h	Holds number of error counter overflow that received by the PRBS checker. Value in this register is locked when write is done to register prbs_status_6 bit[0] or bit[1]. Counter stops on 0xFF. Note: when PRBS counters work in single mode, overflow counter is not active

7.6.2.56 PRBS_CTRL_1 Register (Offset = 619h) [Reset = 0574h]

PRBS_CTRL_1 is shown in Figure 7-73 and described in Table 7-79.

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Figure 7-73 PRBS_CTRL_1 Register

15	14	13	12	11	10	9	8
RESERVED		RESERVED	send_pkt	RESERVED	cfg_prbs_chk_sel
R-0h		R-0h	R/WMC,0-0h	R-0h	R/W-5h

7	6	5	4	3	2	1	0
RESERVED	cfg_prbs_gen_sel			cfg_prbs_cnt_mode	cfg_prbs_chk_enable	cfg_pkt_gen_prbs	pkt_gen_en
R-0h	R/W-7h			R/W-0h	R/W-1h	R/W-0h	R/W-0h

Table 7-79 PRBS_CTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	send_pkt	R/WMC,0	0h	Enables generating MAC packet with fix/incremental data w CRC (pkt_gen_en has to be set and cfg_pkt_gen_prbs has to be clear) Cleared automatically when pkt_done is set 0h = Stop MAC packet 1h = Transmit MAC packet w CRC
11	RESERVED	R	0h	Reserved
10-8	cfg_prbs_chk_sel	R/W	5h	000 : Checker receives from RGMII TX 001 : Checker receives SGMII TX 101 : Checker receives from Cu RX
7	RESERVED	R	0h	Reserved
6-4	cfg_prbs_gen_sel	R/W	7h	000 : PRBS transmits to RGMII RX 001 : PRBS transmits to SGMII RX 101 : PRBS transmits to Cu TX
3	cfg_prbs_cnt_mode	R/W	0h	1 = Continuous mode, when one of the PRBS counters reaches max value, pulse is generated and counter starts counting from zero again 0 = Single mode, When one of the PRBS counters reaches max value, PRBS checker stops counting.
2	cfg_prbs_chk_enable	R/W	1h	Enable PRBS checker xbar (to receive data) To be enabled for counters in 0x63C, 0x63D, 0x63E to work 0h = Disable PRBS checker 1h = Enable PRBS checker
1	cfg_pkt_gen_prbs	R/W	0h	If set: (1) When pkt_gen_en is set, PRBS packets are generated continuously (3) When pkt_gen_en is cleared, PRBS RX checker is still enabled If cleared: (1) When pkt_gen_en is set, non - PRBS packet is generated (3) When pkt_gen_en is cleared, PRBS RX checker is disabled as well 0h = Stop PRBS packet 1h = Transmit PRBS packet
0	pkt_gen_en	R/W	0h	1 = Enable packet/PRBS generator 0 = Disable packet/PRBS generator

7.6.2.57 PRBS_CTRL_2 Register (Offset = 61Ah) [Reset = 05DCh]

PRBS_CTRL_2 is shown in Figure 7-74 and described in Table 7-80.

Return to the Summary Table.

Figure 7-74 PRBS_CTRL_2 Register

15	14	13	12	11	10	9	8
cfg_pkt_len_prbs
R/W-5DCh

7	6	5	4	3	2	1	0
cfg_pkt_len_prbs
R/W-5DCh

Table 7-80 PRBS_CTRL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	cfg_pkt_len_prbs	R/W	5DCh	Length (in bytes) of PRBS packets and MAC packets w CRC

7.6.2.58 PRBS_CTRL_3 Register (Offset = 61Bh) [Reset = 007Dh]

PRBS_CTRL_3 is shown in Figure 7-75 and described in Table 7-81.

Return to the Summary Table.

Figure 7-75 PRBS_CTRL_3 Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
cfg_ipg_len
R/W-7Dh

Table 7-81 PRBS_CTRL_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7-0	cfg_ipg_len	R/W	7Dh	Inter-packet gap (in bytes) between packets

7.6.2.59 PRBS_STATUS_2 Register (Offset = 61Ch) [Reset = 0000h]

PRBS_STATUS_2 is shown in Figure 7-76 and described in Table 7-82.

Return to the Summary Table.

Figure 7-76 PRBS_STATUS_2 Register

15	14	13	12	11	10	9	8
prbs_byte_cnt
R-0h

7	6	5	4	3	2	1	0
prbs_byte_cnt
R-0h

Table 7-82 PRBS_STATUS_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	prbs_byte_cnt	R	0h	Holds number of total bytes that received by the PRBS checker. Value in this register is locked when write is done to register prbs_status_6 bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFF

7.6.2.60 PRBS_STATUS_3 Register (Offset = 61Dh) [Reset = 0000h]

PRBS_STATUS_3 is shown in Figure 7-77 and described in Table 7-83.

Return to the Summary Table.

Figure 7-77 PRBS_STATUS_3 Register

15	14	13	12	11	10	9	8
prbs_pkt_cnt_15_0
R-0h

7	6	5	4	3	2	1	0
prbs_pkt_cnt_15_0
R-0h

Table 7-83 PRBS_STATUS_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	prbs_pkt_cnt_15_0	R	0h	Bits [15:0] of number of total packets received by the PRBS checker Value in this register is locked when write is done to register prbs_status_6 bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF

7.6.2.61 PRBS_STATUS_4 Register (Offset = 61Eh) [Reset = 0000h]

PRBS_STATUS_4 is shown in Figure 7-78 and described in Table 7-84.

Return to the Summary Table.

Figure 7-78 PRBS_STATUS_4 Register

15	14	13	12	11	10	9	8
prbs_pkt_cnt_31_16
R-0h

7	6	5	4	3	2	1	0
prbs_pkt_cnt_31_16
R-0h

Table 7-84 PRBS_STATUS_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	prbs_pkt_cnt_31_16	R	0h	Bits [31:16] of number of total packets received by the PRBS checker Value in this register is locked when write is done to register prbs_status_6 bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF

7.6.2.62 PRBS_STATUS_6 Register (Offset = 620h) [Reset = 0000h]

PRBS_STATUS_6 is shown in Figure 7-79 and described in Table 7-85.

Return to the Summary Table.

Figure 7-79 PRBS_STATUS_6 Register

15	14	13	12	11	10	9	8
RESERVED			pkt_done	pkt_gen_busy	prbs_pkt_ov	prbs_byte_ov	prbs_lock
R-0h			R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
prbs_err_cnt
R-0h

Table 7-85 PRBS_STATUS_6 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0h	Reserved
12	pkt_done	R	0h	Set when all MAC packets w CRC are transmitted 0h = MAC packet transmission in progress 1h = MAC packets transmission completed
11	pkt_gen_busy	R	0h	1 = Packet generator is in process 0 = Packet generator is not in process
10	prbs_pkt_ov	R	0h	If set, packet counter reached overflow Overflow is cleared when PRBS counters are cleared - done by setting bit #1 of prbs_status_6 0h = No overflow 1h = Packet counter overflow
9	prbs_byte_ov	R	0h	If set, bytes counter reached overflow Overflow is cleared when PRBS counters are cleared - done by setting bit #1of prbs_status_6 0h = No overflow 1h = byte counter overflow
8	prbs_lock	R	0h	1 = PRBS checker is locked sync) on received byte stream 0 = PRBS checker is not locked 0h = PRBS checker is not locked 1h = PRBS checker is locked sync) on received byte stream
7-0	prbs_err_cnt	R	0h	Holds number of errored bits received by the PRBS checker Value in this register is locked when write is done to bit[0] or bit[1] When PRBS Count Mode set to zero, count stops on 0xFF Notes: Writing bit 0 generates a lock signal for the PRBS counters. Writing bit 1 generates a lock and clear signal for the PRBS counters

7.6.2.63 PRBS_STATUS_8 Register (Offset = 622h) [Reset = 0000h]

PRBS_STATUS_8 is shown in Figure 7-80 and described in Table 7-86.

Return to the Summary Table.

Figure 7-80 PRBS_STATUS_8 Register

15	14	13	12	11	10	9	8
pkt_err_cnt_15_0
R-0h

7	6	5	4	3	2	1	0
pkt_err_cnt_15_0
R-0h

Table 7-86 PRBS_STATUS_8 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	pkt_err_cnt_15_0	R	0h	Bits [15:0] of number of total packets with error received by the PRBS checker Value in this register is locked when write is done to register prbs_status_6 bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF

7.6.2.64 PRBS_STATUS_9 Register (Offset = 623h) [Reset = 0000h]

PRBS_STATUS_9 is shown in Figure 7-81 and described in Table 7-87.

Return to the Summary Table.

Figure 7-81 PRBS_STATUS_9 Register

15	14	13	12	11	10	9	8
pkt_err_cnt_31_16
R-0h

7	6	5	4	3	2	1	0
pkt_err_cnt_31_16
R-0h

Table 7-87 PRBS_STATUS_9 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	pkt_err_cnt_31_16	R	0h	Bits [31:16] of number of total packets with error received by the PRBS checker Value in this register is locked when write is done to register prbs_status_6 bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF

7.6.2.65 PRBS_CTRL_4 Register (Offset = 624h) [Reset = 5511h]

PRBS_CTRL_4 is shown in Figure 7-82 and described in Table 7-88.

Return to the Summary Table.

Figure 7-82 PRBS_CTRL_4 Register

15	14	13	12	11	10	9	8
cfg_pkt_data
R/W-55h

7	6	5	4	3	2	1	0
cfg_pkt_mode		cfg_pattern_vld_bytes			cfg_pkt_cnt
R/W-0h		R/W-2h			R/W-1h

Table 7-88 PRBS_CTRL_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	cfg_pkt_data	R/W	55h	Fixed data to be sent in Fix data mode
7-6	cfg_pkt_mode	R/W	0h	0h = Incremental 1h = Fixed 2h = PRBS 3h = PRBS
5-3	cfg_pattern_vld_bytes	R/W	2h	Number of bytes of valid pattern in packet (Max - 6) 0h = 0 bytes 1h = 1 bytes 2h = 2 bytes 3h = 3 bytes 4h = 4 bytes 5h = 5 bytes 6h = 6 bytes 7h = 6 bytes
2-0	cfg_pkt_cnt	R/W	1h	000b = 1 packet 001b = 10 packets 010b = 100 packets 011b = 1000 packets 100b = 10000 packets 101b = 100000 packets 110b = 1000000 packets 111b = Continuous packets

7.6.2.66 PRBS_CTRL_5 Register (Offset = 625h) [Reset = 0000h]

PRBS_CTRL_5 is shown in Figure 7-83 and described in Table 7-89.

Return to the Summary Table.

Figure 7-83 PRBS_CTRL_5 Register

15	14	13	12	11	10	9	8
pattern_15_0
R/W-0h

7	6	5	4	3	2	1	0
pattern_15_0
R/W-0h

Table 7-89 PRBS_CTRL_5 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	pattern_15_0	R/W	0h	Bits 15:0 of pattern

7.6.2.67 PRBS_CTRL_6 Register (Offset = 626h) [Reset = 0000h]

PRBS_CTRL_6 is shown in Figure 7-84 and described in Table 7-90.

Return to the Summary Table.

Figure 7-84 PRBS_CTRL_6 Register

15	14	13	12	11	10	9	8
pattern_31_16
R/W-0h

7	6	5	4	3	2	1	0
pattern_31_16
R/W-0h

Table 7-90 PRBS_CTRL_6 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	pattern_31_16	R/W	0h	Bits 31:16 of pattern

7.6.2.68 PRBS_CTRL_7 Register (Offset = 627h) [Reset = 0000h]

PRBS_CTRL_7 is shown in Figure 7-85 and described in Table 7-91.

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Figure 7-85 PRBS_CTRL_7 Register

15	14	13	12	11	10	9	8
pattern_47_32
R/W-0h

7	6	5	4	3	2	1	0
pattern_47_32
R/W-0h

Table 7-91 PRBS_CTRL_7 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	pattern_47_32	R/W	0h	Bits 47:32 of pattern

7.6.2.69 PRBS_CTRL_8 Register (Offset = 628h) [Reset = 0000h]

PRBS_CTRL_8 is shown in Figure 7-86 and described in Table 7-92.

Return to the Summary Table.

Figure 7-86 PRBS_CTRL_8 Register

15	14	13	12	11	10	9	8
pmatch_data_15_0
R/W-0h

7	6	5	4	3	2	1	0
pmatch_data_15_0
R/W-0h

Table 7-92 PRBS_CTRL_8 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	pmatch_data_15_0	R/W	0h	Bits 15:0 of Perfect Match Data - used for DA (destination address) match

7.6.2.70 PRBS_CTRL_9 Register (Offset = 629h) [Reset = 0000h]

PRBS_CTRL_9 is shown in Figure 7-87 and described in Table 7-93.

Return to the Summary Table.

Figure 7-87 PRBS_CTRL_9 Register

15	14	13	12	11	10	9	8
pmatch_data_31_16
R/W-0h

7	6	5	4	3	2	1	0
pmatch_data_31_16
R/W-0h

Table 7-93 PRBS_CTRL_9 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	pmatch_data_31_16	R/W	0h	Bits 31:16 of Perfect Match Data - used for DA (destination address) match

7.6.2.71 PRBS_CTRL_10 Register (Offset = 62Ah) [Reset = 0000h]

PRBS_CTRL_10 is shown in Figure 7-88 and described in Table 7-94.

Return to the Summary Table.

Figure 7-88 PRBS_CTRL_10 Register

15	14	13	12	11	10	9	8
pmatch_data_47_32
R/W-0h

7	6	5	4	3	2	1	0
pmatch_data_47_32
R/W-0h

Table 7-94 PRBS_CTRL_10 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	pmatch_data_47_32	R/W	0h	Bits 47:32 of Perfect Match Data - used for DA (destination address) match

7.6.2.72 CRC_STATUS Register (Offset = 638h) [Reset = 0000h]

CRC_STATUS is shown in Figure 7-89 and described in Table 7-95.

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Figure 7-89 CRC_STATUS Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						rx_bad_crc	tx_bad_crc
R-0h						R-0h	R-0h

Table 7-95 CRC_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-2	RESERVED	R	0h	Reserved
1	rx_bad_crc	R	0h	CRC error indication in packet received on Cu RX 0h = No CRC error 1h = CRC error
0	tx_bad_crc	R	0h	CRC error indication in packet transmitted on Cu TX 0h = No CRC error 1h = CRC error

7.6.2.73 PKT_STAT_1 Register (Offset = 639h) [Reset = 0000h]

PKT_STAT_1 is shown in Figure 7-90 and described in Table 7-96.

Return to the Summary Table.

Figure 7-90 PKT_STAT_1 Register

15	14	13	12	11	10	9	8
tx_pkt_cnt_15_0
R-0h

7	6	5	4	3	2	1	0
tx_pkt_cnt_15_0
R-0h

Table 7-96 PKT_STAT_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	tx_pkt_cnt_15_0	R	0h	Lower 16 bits of Tx packet counter Note : Register is cleared when 0x639, 0x63A, 0x63B are read in sequence

7.6.2.74 PKT_STAT_2 Register (Offset = 63Ah) [Reset = 0000h]

PKT_STAT_2 is shown in Figure 7-91 and described in Table 7-97.

Return to the Summary Table.

Figure 7-91 PKT_STAT_2 Register

15	14	13	12	11	10	9	8
tx_pkt_cnt_31_16
R-0h

7	6	5	4	3	2	1	0
tx_pkt_cnt_31_16
R-0h

Table 7-97 PKT_STAT_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	tx_pkt_cnt_31_16	R	0h	Upper 16 bits of Tx packet counter Note : Register is cleared when 0x639, 0x63A, 0x63B are read in sequence

7.6.2.75 PKT_STAT_3 Register (Offset = 63Bh) [Reset = 0000h]

PKT_STAT_3 is shown in Figure 7-92 and described in Table 7-98.

Return to the Summary Table.

Figure 7-92 PKT_STAT_3 Register

15	14	13	12	11	10	9	8
tx_err_pkt_cnt
R-0h

7	6	5	4	3	2	1	0
tx_err_pkt_cnt
R-0h

Table 7-98 PKT_STAT_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	tx_err_pkt_cnt	R	0h	Tx packet w error (CRC error) counter Note : Register is cleared when 0x639, 0x63A, 0x63B are read in sequence

7.6.2.76 PKT_STAT_4 Register (Offset = 63Ch) [Reset = 0000h]

PKT_STAT_4 is shown in Figure 7-93 and described in Table 7-99.

Return to the Summary Table.

Figure 7-93 PKT_STAT_4 Register

15	14	13	12	11	10	9	8
rx_pkt_cnt_15_0
R-0h

7	6	5	4	3	2	1	0
rx_pkt_cnt_15_0
R-0h

Table 7-99 PKT_STAT_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	rx_pkt_cnt_15_0	R	0h	Lower 16 bits of Rx packet counter Note : Register is cleared when 0x63C, 0x63D, 0x63E are read in sequence

7.6.2.77 PKT_STAT_5 Register (Offset = 63Dh) [Reset = 0000h]

PKT_STAT_5 is shown in Figure 7-94 and described in Table 7-100.

Return to the Summary Table.

Figure 7-94 PKT_STAT_5 Register

15	14	13	12	11	10	9	8
rx_pkt_cnt_31_16
R-0h

7	6	5	4	3	2	1	0
rx_pkt_cnt_31_16
R-0h

Table 7-100 PKT_STAT_5 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	rx_pkt_cnt_31_16	R	0h	Upper 16 bits of Rx packet counter Note : Register is cleared when 0x63C, 0x63D, 0x63E are read in sequence

7.6.2.78 PKT_STAT_6 Register (Offset = 63Eh) [Reset = 0000h]

PKT_STAT_6 is shown in Figure 7-95 and described in Table 7-101.

Return to the Summary Table.

Figure 7-95 PKT_STAT_6 Register

15	14	13	12	11	10	9	8
rx_err_pkt_cnt
R-0h

7	6	5	4	3	2	1	0
rx_err_pkt_cnt
R-0h

Table 7-101 PKT_STAT_6 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	rx_err_pkt_cnt	R	0h	Rx packet w error (CRC error) counter Note : Register is cleared when 0x63C, 0x63D, 0x63E are read in sequence

7.6.2.79 SQI_REG_1 Register (Offset = 871h) [Reset = 0000h]

SQI_REG_1 is shown in Figure 7-96 and described in Table 7-102.

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Figure 7-96 SQI_REG_1 Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
worst_sqi_out			RESERVED	sqi_out			RESERVED
R-0h			R-0h	R-0h			R-0h

Table 7-102 SQI_REG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7-5	worst_sqi_out	R	0h	3 bit Worst SQI since last read (see SQI mapping above) Cleared on Read
4	RESERVED	R	0h	Reserved
3-1	sqi_out	R	0h	3 bit SQI - (mse here refers to Mean Square Error 0x875[9:0]) 0b000 = MSE > 102 0b001 = 81 < MSE ≤102 0b010 = 65 < MSE ≤ 81 0b011 = 51 < MSE ≤ 65 0b100 = 41 < MSE ≤ 51 0b101 = 32 < MSE ≤ 41 0b110 = 25 < MSE ≤ 32 0b111 = MSE ≤ 25
0	RESERVED	R	0h	Reserved

7.6.2.80 DSP_REG_74 Register (Offset = 874h) [Reset = 0000h]

DSP_REG_74 is shown in Figure 7-97 and described in Table 7-103.

Return to the Summary Table.

Figure 7-97 DSP_REG_74 Register

15	14	13	12	11	10	9	8
worst_peak_mse_out
R-0h

7	6	5	4	3	2	1	0
peak_mse_out
R-0h

Table 7-103 DSP_REG_74 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	worst_peak_mse_out	R	0h	Worst peak mse out since last read as per TC12 (see peak mse mapping above) Cleared on Read
7-0	peak_mse_out	R	0h	Peak mse as per TC12 - This value is 0.0625*averaged squared slicer error(max val = 0.015625). To get actual squared slicer error divide this value by 248.

7.6.2.81 DSP_REG_75 Register (Offset = 875h) [Reset = 0000h]

DSP_REG_75 is shown in Figure 7-98 and described in Table 7-104.

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Figure 7-98 DSP_REG_75 Register

15	14	13	12	11	10	9	8
RESERVED				RESERVED		mse_lock
R-0h				R-0h		R-0h

7	6	5	4	3	2	1	0
mse_lock
R-0h

Table 7-104 DSP_REG_75 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reserved
11-10	RESERVED	R	0h	Reserved
9-0	mse_lock	R	0h	10 bit mse used for SQI mapping. (mse = mean square error at the receiver)

7.6.2.82 PMA_PMD_CONTROL_1 Register (Offset = 1000h) [Reset = 0000h]

PMA_PMD_CONTROL_1 is shown in Figure 7-99 and described in Table 7-105.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-99 PMA_PMD_CONTROL_1 Register

15	14	13	12	11	10	9	8
pma_reset_2	RESERVED			RESERVED	RESERVED
R-0h	R-0h			R-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 7-105 PMA_PMD_CONTROL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	pma_reset_2	R	0h	1 = PMA/PMD reset 0 = Normal operation Note - RW bit, self clearing
14-12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10-0	RESERVED	R	0h	Reserved

7.6.2.83 PMA_PMD_CONTROL_2 Register (Offset = 1007h) [Reset = 003Dh]

PMA_PMD_CONTROL_2 is shown in Figure 7-100 and described in Table 7-106.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-100 PMA_PMD_CONTROL_2 Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED		cfg_pma_type_selection
R-0h		R/W-3Dh

Table 7-106 PMA_PMD_CONTROL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-6	RESERVED	R	0h	Reserved
5-0	cfg_pma_type_selection	R/W	3Dh	BASE-T1 type selection for device 3Dh = BASE-T1 type selection for device

7.6.2.84 PMA_PMD_TRANSMIT_DISABLE Register (Offset = 1009h) [Reset = 0000h]

PMA_PMD_TRANSMIT_DISABLE is shown in Figure 7-101 and described in Table 7-107.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-101 PMA_PMD_TRANSMIT_DISABLE Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							cfg_transmit_disable_2
R-0h							R-0h

Table 7-107 PMA_PMD_TRANSMIT_DISABLE Register Field Descriptions

Bit	Field	Type	Reset	Description
15-1	RESERVED	R	0h	Reserved
0	cfg_transmit_disable_2	R	0h	1 = Transmit disable 0 = Normal operation Note - RW bit

7.6.2.85 PMA_PMD_EXTENDED_ABILITY2 Register (Offset = 100Bh) [Reset = 0800h]

PMA_PMD_EXTENDED_ABILITY2 is shown in Figure 7-102 and described in Table 7-108.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-102 PMA_PMD_EXTENDED_ABILITY2 Register

15	14	13	12	11	10	9	8
RESERVED				base_t1_extended_abilities	RESERVED
R-0h				R-1h	R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 7-108 PMA_PMD_EXTENDED_ABILITY2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reserved
11	base_t1_extended_abilities	R	1h	1 = PMA/PMD has BASE-T1 extended abilities listed in register 1.18 0 = PMA/PMD does not have BASE-T1 extended abilities
10-0	RESERVED	R	0h	Reserved

7.6.2.86 PMA_PMD_EXTENDED_ABILITY Register (Offset = 1012h) [Reset = 0002h]

PMA_PMD_EXTENDED_ABILITY is shown in Figure 7-103 and described in Table 7-109.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-103 PMA_PMD_EXTENDED_ABILITY Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						mr_1000_base_t1_ability	mr_100_base_t1_ability
R-0h						R-1h	R-0h

Table 7-109 PMA_PMD_EXTENDED_ABILITY Register Field Descriptions

Bit	Field	Type	Reset	Description
15-2	RESERVED	R	0h	Reserved
1	mr_1000_base_t1_ability	R	1h	1 = PMA/PMD is able to perform 1000BASE-T1 0 = PMA/PMD is not able to perform 1000BASE-T1
0	mr_100_base_t1_ability	R	0h	1 = PMA/PMD is able to perform 100BASE-T1 0 = PMA/PMD is not able to perform 100BASE-T1

7.6.2.87 PMA_PMD_CONTROL Register (Offset = 1834h) [Reset = 8001h]

PMA_PMD_CONTROL is shown in Figure 7-104 and described in Table 7-110.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-104 PMA_PMD_CONTROL Register

15	14	13	12	11	10	9	8
RESERVED	cfg_master_slave_val	RESERVED
R-0h	R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED				RESERVED
R-0h				R-0h

Table 7-110 PMA_PMD_CONTROL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	cfg_master_slave_val	R/W	0h	1 = Configure PHY as MASTER 0 = Configure PHY as SLAVE
13-4	RESERVED	R	0h	Reserved
3-0	RESERVED	R	0h	Reserved

7.6.2.88 PMA_CONTROL Register (Offset = 1900h) [Reset = 0000h]

PMA_CONTROL is shown in Figure 7-105 and described in Table 7-111.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-105 PMA_CONTROL Register

15	14	13	12	11	10	9	8
pma_reset	cfg_transmit_disable	RESERVED		RESERVED	RESERVED
R-0h	R-0h	R-0h		R-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 7-111 PMA_CONTROL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	pma_reset	R	0h	1 = PMA/PMD reset 0 = Normal operation Note - RW bit, self clearing
14	cfg_transmit_disable	R	0h	1 = Transmit disable 0 = Normal operation Note - RW bit
13-12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10-0	RESERVED	R	0h	Reserved

7.6.2.89 PMA_STATUS Register (Offset = 1901h) [Reset = 0900h]

PMA_STATUS is shown in Figure 7-106 and described in Table 7-112.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-106 PMA_STATUS Register

15	14	13	12	11	10	9	8
RESERVED				oam_ability	eee_ability	receive_fault_ability	low_power_ability
R-0h				R-1h	R-0h	R-0h	R-1h

7	6	5	4	3	2	1	0
RESERVED					receive_polarity	receive_fault	pma_receive_link_status_ll
R-0h					R-0h	R-0h	R/W0S-0h

Table 7-112 PMA_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reserved
11	oam_ability	R	1h	1 = PHY has 1000BASE-T1 OAM ability 0 = PHY does not have 1000BASE-T1 OAM ability
10	eee_ability	R	0h	1 = PHY has EEE ability 0 = PHY does not have EEE ability
9	receive_fault_ability	R	0h	1 = PMA/PMD has the ability to detect a fault condition on the receive path 0 = PMA/PMD does not have the ability to detect a fault condition on the receive path
8	low_power_ability	R	1h	1 = PMA/PMD has low-power ability 0 = PMA/PMD does not have low-power ability
7-3	RESERVED	R	0h	Reserved
2	receive_polarity	R	0h	1 = Receive polarity is reversed 0 = Receive polarity is not reversed
1	receive_fault	R	0h	1 = Fault condition detected 0 = Fault condition not detected
0	pma_receive_link_status_ll	R/W0S	0h	1 = PMA/PMD receive link up 0 = PMA/PMD receive link down

7.6.2.90 TRAINING Register (Offset = 1902h) [Reset = 0002h]

TRAINING is shown in Figure 7-107 and described in Table 7-113.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-107 TRAINING Register

15	14	13	12	11	10	9	8
RESERVED					cfg_training_user_fld
R-0h					R/W-0h

7	6	5	4	3	2	1	0
cfg_training_user_fld				RESERVED		cfg_oam_en	cfg_eee_en
R/W-0h				R-0h		R/W-1h	R/W-0h

Table 7-113 TRAINING Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	0h	Reserved
10-4	cfg_training_user_fld	R/W	0h	7-bit user defined field to send to the link partner
3-2	RESERVED	R	0h	Reserved
1	cfg_oam_en	R/W	1h	1 = 1000BASE-T1 OAM ability advertised to link partner 0 = 1000BASE-T1 OAM ability not advertised to link partner
0	cfg_eee_en	R/W	0h	1 = EEE ability advertised to link partner 0 = EEE ability not advertised to link partner

7.6.2.91 LP_TRAINING Register (Offset = 1903h) [Reset = 0000h]

LP_TRAINING is shown in Figure 7-108 and described in Table 7-114.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-108 LP_TRAINING Register

15	14	13	12	11	10	9	8
RESERVED					lp_training_user_fld
R-0h					R-0h

7	6	5	4	3	2	1	0
lp_training_user_fld				RESERVED		lp_oam_adv	lp_eee_adv
R-0h				R-0h		R-0h	R-0h

Table 7-114 LP_TRAINING Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	0h	Reserved
10-4	lp_training_user_fld	R	0h	7-bit user defined field received from the link partner
3-2	RESERVED	R	0h	Reserved
1	lp_oam_adv	R	0h	1 = Link partner has 1000BASE-T1 OAM ability 0 = Link partner does not have 1000BASE-T1 OAM ability
0	lp_eee_adv	R	0h	1 = Link partner has EEE ability 0 = Link partner does not have EEE ability

7.6.2.92 TEST_MODE_CONTROL Register (Offset = 1904h) [Reset = 0000h]

TEST_MODE_CONTROL is shown in Figure 7-109 and described in Table 7-115.

Return to the Summary Table.

First nibble (0x1) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-109 TEST_MODE_CONTROL Register

15	14	13	12	11	10	9	8
cfg_test_mode			RESERVED
R/W-0h			R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 7-115 TEST_MODE_CONTROL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	cfg_test_mode	R/W	0h	111 = Test mode 7 110 = Test mode 6 101 = Test mode 5 100 = Test mode 4 011 = Reserved 010 = Test mode 2 001 = Test mode 1 000 = Normal (non-test) operation
12-0	RESERVED	R	0h	Reserved

7.6.2.93 PCS_CONTROL Register (Offset = 3900h) [Reset = 0000h]

PCS_CONTROL is shown in Figure 7-110 and described in Table 7-116.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-110 PCS_CONTROL Register

15	14	13	12	11	10	9	8
pcs_reset	RESERVED	RESERVED
R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 7-116 PCS_CONTROL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	pcs_reset	R	0h	Note - RW bit, self clear bit 0h = Normal operation 1h = PCS reset
14	RESERVED	R	0h	Reserved
13-0	RESERVED	R	0h	Reserved

7.6.2.94 PCS_STATUS Register (Offset = 3901h) [Reset = 0000h]

PCS_STATUS is shown in Figure 7-111 and described in Table 7-117.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-111 PCS_STATUS Register

15	14	13	12	11	10	9	8
RESERVED				RESERVED	RESERVED	RESERVED	RESERVED
R-0h				R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
pcs_fault	RESERVED				pcs_receive_link_status_ll	RESERVED
R-0h	R-0h				R/W0S-0h	R-0h

Table 7-117 PCS_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7	pcs_fault	R	0h	0h = No fault condition detected 1h = Fault condition detected
6-3	RESERVED	R	0h	Reserved
2	pcs_receive_link_status_ll	R/W0S	0h	0h = PCS receive link down 1h = PCS receive link up
1-0	RESERVED	R	0h	Reserved

7.6.2.95 PCS_STATUS_2 Register (Offset = 3902h) [Reset = 0000h]

PCS_STATUS_2 is shown in Figure 7-112 and described in Table 7-118.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-112 PCS_STATUS_2 Register

15	14	13	12	11	10	9	8
RESERVED					pcs_receive_link_status	hi_rfer	block_lock
R-0h					R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
hi_rfer_lh	block_lock_ll	RESERVED
R/W0C-0h	R/W0S-0h	R-0h

Table 7-118 PCS_STATUS_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	0h	Reserved
10	pcs_receive_link_status	R	0h	0h = PCS receive link down 1h = PCS receive link up
9	hi_rfer	R	0h	0h = PCS not reporting a high BER 1h = PCS reporting a high BER
8	block_lock	R	0h	0h = PCS not locked to received blocks 1h = PCS locked to received blocks
7	hi_rfer_lh	R/W0C	0h	0h = PCS has not reported a high BER 1h = PCS has reported a high BER
6	block_lock_ll	R/W0S	0h	0h = PCS does not have block lock 1h = PCS has block lock
5-0	RESERVED	R	0h	Reserved

7.6.2.96 OAM_TRANSMIT Register (Offset = 3904h) [Reset = 0000h]

OAM_TRANSMIT is shown in Figure 7-113 and described in Table 7-119.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-113 OAM_TRANSMIT Register

15	14	13	12	11	10	9	8
mr_tx_valid	mr_tx_toggle	mr_tx_received	mr_tx_received_toggle	mr_tx_message_num
R/WMC,0-0h	R-0h	R-0h	R-0h	R/W-0h

7	6	5	4	3	2	1	0
RESERVED				mr_rx_ping	mr_tx_ping	mr_tx_snr
R-0h				R-0h	R/W-0h	R-0h

Table 7-119 OAM_TRANSMIT Register Field Descriptions

Bit	Field	Type	Reset	Description
15	mr_tx_valid	R/WMC,0	0h	This bit is used to indicate message data in registers 3.2308.11:8, 3.2309, 3.2310, 3.2311, and 3.2312 are valid and ready to be loaded. This bit shall self-clear when registers are loaded by the state machine. 1 = Message data in registers are valid 0 = Message data in registers are not valid
14	mr_tx_toggle	R	0h	Toggle value to be transmitted with message. This bit is set by the state machine and cannot be overridden by the user.
13	mr_tx_received	R	0h	This bit shall self clear on read. 1 = 1000BASE-T1 OAM message received by link partner 0 = 1000BASE-T1 OAM message not received by link partner
12	mr_tx_received_toggle	R	0h	Toggle value of message that was received by link partner
11-8	mr_tx_message_num	R/W	0h	User-defined message number to send
7-4	RESERVED	R	0h	Reserved
3	mr_rx_ping	R	0h	Received PingTx value from latest good 1000BASE-T1 OAM frame received
2	mr_tx_ping	R/W	0h	Ping value to send to link partner
1-0	mr_tx_snr	R	0h	00 = PHY link is failing and shall drop link and relink within 2ms to 4ms after the end of the current 1000BASE-T1 OAM frame. 01 = LPI refresh is insufficient to maintain PHY SNR. Request link partner to exit LPI and send idles (used only when EEE is enabled). 10 = PHY SNR is marginal. 11 = PHY SNR is good.

7.6.2.97 OAM_TX_MESSAGE_1 Register (Offset = 3905h) [Reset = 0000h]

OAM_TX_MESSAGE_1 is shown in Figure 7-114 and described in Table 7-120.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-114 OAM_TX_MESSAGE_1 Register

15	14	13	12	11	10	9	8
mr_tx_message_15_0
R/W-0h

7	6	5	4	3	2	1	0
mr_tx_message_15_0
R/W-0h

Table 7-120 OAM_TX_MESSAGE_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	mr_tx_message_15_0	R/W	0h	Message octet 1/0. LSB transmitted first.

7.6.2.98 OAM_TX_MESSAGE_2 Register (Offset = 3906h) [Reset = 0000h]

OAM_TX_MESSAGE_2 is shown in Figure 7-115 and described in Table 7-121.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-115 OAM_TX_MESSAGE_2 Register

15	14	13	12	11	10	9	8
mr_tx_message_31_16
R/W-0h

7	6	5	4	3	2	1	0
mr_tx_message_31_16
R/W-0h

Table 7-121 OAM_TX_MESSAGE_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	mr_tx_message_31_16	R/W	0h	Message octet 3/2. LSB transmitted first.

7.6.2.99 OAM_TX_MESSAGE_3 Register (Offset = 3907h) [Reset = 0000h]

OAM_TX_MESSAGE_3 is shown in Figure 7-116 and described in Table 7-122.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-116 OAM_TX_MESSAGE_3 Register

15	14	13	12	11	10	9	8
mr_tx_message_47_32
R/W-0h

7	6	5	4	3	2	1	0
mr_tx_message_47_32
R/W-0h

Table 7-122 OAM_TX_MESSAGE_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	mr_tx_message_47_32	R/W	0h	Message octet 5/4. LSB transmitted first.

7.6.2.100 OAM_TX_MESSAGE_4 Register (Offset = 3908h) [Reset = 0000h]

OAM_TX_MESSAGE_4 is shown in Figure 7-117 and described in Table 7-123.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-117 OAM_TX_MESSAGE_4 Register

15	14	13	12	11	10	9	8
mr_tx_message_63_48
R/W-0h

7	6	5	4	3	2	1	0
mr_tx_message_63_48
R/W-0h

Table 7-123 OAM_TX_MESSAGE_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	mr_tx_message_63_48	R/W	0h	Message octet 7/6. LSB transmitted first.

7.6.2.101 OAM_RECEIVE Register (Offset = 3909h) [Reset = 0000h]

OAM_RECEIVE is shown in Figure 7-118 and described in Table 7-124.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-118 OAM_RECEIVE Register

15	14	13	12	11	10	9	8
mr_rx_lp_valid	mr_rx_lp_toggle	RESERVED		mr_rx_lp_message_num
R-0h	R-0h	R-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED						mr_rx_lp_SNR
R-0h						R-0h

Table 7-124 OAM_RECEIVE Register Field Descriptions

Bit	Field	Type	Reset	Description
15	mr_rx_lp_valid	R	0h	This bit is used to indicate message data in registers 3.2313.11:8, 3.2314, 3.2315, 3.2316, and 3.2317 are stored and ready to be read. This bit shall self clear when register 3.2317 is read. 0h = Message data in registers are not valid 1h = Message data in registers are valid
14	mr_rx_lp_toggle	R	0h	Toggle value received with message Note - 0x3 added in [15:12] to differentiate
13-12	RESERVED	R	0h	Reserved
11-8	mr_rx_lp_message_num	R	0h	Message number from link partner Note - 0x3 added in [15:12] to differentiate
7-2	RESERVED	R	0h	Reserved
1-0	mr_rx_lp_SNR	R	0h	00 = Link partner link is failing and shall drop link and relink within 2ms to 4ms after the end of the current 1000BASE-T1 OAM frame. 01 = LPI refresh is insufficient to maintain link partner SNR. Link partner requests local device to exit LPI and send idles (used only when EEE is enabled). 10 = Link partner SNR is marginal. 11 = Link partner SNR is good

7.6.2.102 OAM_RX_MESSAGE_1 Register (Offset = 390Ah) [Reset = 0000h]

OAM_RX_MESSAGE_1 is shown in Figure 7-119 and described in Table 7-125.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-119 OAM_RX_MESSAGE_1 Register

15	14	13	12	11	10	9	8
mr_rx_lp_message_15_0
R-0h

7	6	5	4	3	2	1	0
mr_rx_lp_message_15_0
R-0h

Table 7-125 OAM_RX_MESSAGE_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	mr_rx_lp_message_15_0	R	0h	Message octet 1/0. LSB transmitted first.

7.6.2.103 OAM_RX_MESSAGE_2 Register (Offset = 390Bh) [Reset = 0000h]

OAM_RX_MESSAGE_2 is shown in Figure 7-120 and described in Table 7-126.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-120 OAM_RX_MESSAGE_2 Register

15	14	13	12	11	10	9	8
mr_rx_lp_message_31_16
R-0h

7	6	5	4	3	2	1	0
mr_rx_lp_message_31_16
R-0h

Table 7-126 OAM_RX_MESSAGE_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	mr_rx_lp_message_31_16	R	0h	Message octet 3/2. LSB transmitted first.

7.6.2.104 OAM_RX_MESSAGE_3 Register (Offset = 390Ch) [Reset = 0000h]

OAM_RX_MESSAGE_3 is shown in Figure 7-121 and described in Table 7-127.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-121 OAM_RX_MESSAGE_3 Register

15	14	13	12	11	10	9	8
mr_rx_lp_message_47_32
R-0h

7	6	5	4	3	2	1	0
mr_rx_lp_message_47_32
R-0h

Table 7-127 OAM_RX_MESSAGE_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	mr_rx_lp_message_47_32	R	0h	Message octet 5/4. LSB transmitted first.

7.6.2.105 OAM_RX_MESSAGE_4 Register (Offset = 390Dh) [Reset = 0000h]

OAM_RX_MESSAGE_4 is shown in Figure 7-122 and described in Table 7-128.

Return to the Summary Table.

First nibble (0x3) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-122 OAM_RX_MESSAGE_4 Register

15	14	13	12	11	10	9	8
mr_rx_lp_message_63_48
R-0h

7	6	5	4	3	2	1	0
mr_rx_lp_message_63_48
R-0h

Table 7-128 OAM_RX_MESSAGE_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	mr_rx_lp_message_63_48	R	0h	Message octet 7/6. LSB transmitted first.

7.6.2.106 AN_CFG Register (Offset = 7200h) [Reset = 0000h]

AN_CFG is shown in Figure 7-123 and described in Table 7-129.

Return to the Summary Table.

First nibble (0x7) in the register address is to indicate MMD register space. For register access, ignore the first nibble.

Figure 7-123 AN_CFG Register

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							mr_main_reset
R-0h							R/WSC-0h

Table 7-129 AN_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-1	RESERVED	R	0h	Reserved
0	mr_main_reset	R/WSC	0h	1 = Reset link sync/autoneg Note - RW bit