The DS160PR810 internal registers can be accessed through standard SMBus protocol. The DS160PR810 features two banks of channels, Bank 0 (Channels 0- 3) and Bank 1 (Channels 4-7), each featuring a separate register set and requiring a unique SMBus secondary address. The SMBus secondary address pairs (one for each channel bank) are determined at power up based on the configuration of the EQ0_0 / ADDR1 and EQ1_0 / ADDR0 pins. The pin state is read on power up, after the internal power-on reset signal is deasserted.

The EQ0_0 / ADDR1 and EQ1_0 / ADDR0 pins along with the MODE, GAIN0, GAIN1, EQ0_1, EQ1_1, and RX_DET pins are 4-level input pins that are used to control the configuration of the device. These 4-level inputs use a resistor divider to help set the four valid levels as shown in Table 1-1.

There are 16 unique SMBus secondary address pairs (one address for each channel bank) that can be assigned to the device by placing external resistor straps on the EQ0_0 / ADDR1 and EQ1_0 / ADDR0 pins as shown in Table 1-2. When multiple DS160PR810 devices are on the same SMBus interface bus, each channel bank of each device must be configured with a unique SMBus secondary address pair.