SNOSDC1A June   2024  – October 2024 LMH1229 , LMH1239

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements for Serial Management (SM) Bus Interface
    7. 5.7 Timing Requirements for Serial Parallel Interface (SPI) Interface
    8. 5.8 Typical Characteristics
      1. 5.8.1 TX Characteristics
      2. 5.8.2 RX Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Level Input Pins and Thresholds
      2. 6.3.2 Input and Output Signal Flow Control
        1. 6.3.2.1 Input Mux Selection (LMH1239 Only)
        2. 6.3.2.2 Output Mux and SDI_OUT Selection
      3. 6.3.3 Input Carrier Detect
      4. 6.3.4 Adaptive Cable Equalizer (SDI_IN±, SDI_IN1±)
      5. 6.3.5 Clock and Data (CDR) Recovery
      6. 6.3.6 CDR Loop Bandwidth Control
      7. 6.3.7 Output Function Control
      8. 6.3.8 Output Driver Control
        1. 6.3.8.1 Line-Side 75Ω Output Cable Driver (SDI_OUT±)
          1. 6.3.8.1.1 Output Amplitude (VOD)
          2. 6.3.8.1.2 Output Pre-Emphasis
          3. 6.3.8.1.3 Output Slew Rate
          4. 6.3.8.1.4 Output Polarity Inversion
        2. 6.3.8.2 Host-Side 100Ω Output Driver (OUT0±, OUT1±)
      9. 6.3.9 Debug and Diagnostic Features
        1. 6.3.9.1 Internal Eye Opening Monitor (EOM)
        2. 6.3.9.2 PRBS Generator, Error Checker, and Error Injector
        3. 6.3.9.3 Status Indicators and Interrupts
          1. 6.3.9.3.1 LOCK_N (Lock Indicator)
          2. 6.3.9.3.2 CD_N (Carrier Detect)
          3. 6.3.9.3.3 Cable Fault Detection (SDI_OUT+ Only)
          4. 6.3.9.3.4 INT_N (Interrupt)
        4. 6.3.9.4 Additional Programmability
          1. 6.3.9.4.1 Cable EQ Index (CEI)
          2. 6.3.9.4.2 Digital MUTEREF
    4. 6.4 Device Functional Modes
      1. 6.4.1 System Management Bus (SMBus) Mode
        1. 6.4.1.1 SMBus Read and Write Transaction
          1. 6.4.1.1.1 SMBus Write Operation Format
          2. 6.4.1.1.2 SMBus Read Operation Format
      2. 6.4.2 Serial Peripheral Interface (SPI) Mode
        1. 6.4.2.1 SPI Read and Write Transactions
          1. 6.4.2.1.1 SPI Write Transaction Format
          2. 6.4.2.1.2 SPI Read Transaction Format
        2. 6.4.2.2 SPI Daisy Chain
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 SMPTE Requirements and Specifications
      2. 7.1.2 Optimizing the Time to Adapt and Lock
      3. 7.1.3 Optimized Loop Bandwidth Settings for Diagnostic or Cascade Applications
      4. 7.1.4 LMH1229 and LMH1297 (EQ Mode) Pin-to-Pin Compatibility
    2. 7.2 Typical Application
      1. 7.2.1 Cable Equalizer With Loop-Through
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Cable Equalizer With Redundant SDI Input (LMH1239 only)
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Board Stack-Up and Ground References
        2. 7.4.1.2 High-Speed PCB Trace Routing and Coupling
          1. 7.4.1.2.1 SDI_IN± and SDI_OUT±:
          2. 7.4.1.2.2 OUT0± and OUT1±:
        3. 7.4.1.3 Anti-Pads
        4. 7.4.1.4 BNC Connector Layout and Routing
        5. 7.4.1.5 Power Supply and Ground Connections
        6. 7.4.1.6 Footprint Recommendations
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.1.4 LMH1229 and LMH1297 (EQ Mode) Pin-to-Pin Compatibility

The LMH1229 pinout and footprint is compatible with the LMH1297 (12G-SDI Bidirectional I/O with Integrated Reclocker) when the LMH1297 is used in EQ mode. This pin compatibility enables an easy upgrade path for improved SDI cable reach performance. A summary of pinout differences is shown in Figure 7-1.

LMH1229 LMH1239 LMH1219 vs. LMH1297 Pinout Differences Figure 7-1 LMH1219 vs. LMH1297 Pinout Differences
Legend
No special provisions needed
Minor pin setting differences
Major pin setting and definition differences

For a detailed comparison of device pin functionality, refer to Table 7-1.

Table 7-1 LMH1229 vs. LMH1297 (EQ Mode) Pin-to-Pin Comparison
PIN NO. LMH1229 LMH1297 DIFFERENCE SUMMARY(1)
1 SDI_IN+ SDI_IO+ None
2 SDI_IN- SDI_IO-
8 SDI_OUT+ SDI_OUT+ None
7 SDI_OUT- SDI_OUT-
23 OUT0+ OUT0+ None
22 OUT0- OUT0-
19 OUT1+ IN0+ LMH1229: Secondary 100Ω PCB output.
LMH1297: Don't care. Pins are unused in EQ mode.
For pin compatible functionality: Leave floating.
18 OUT1- IN0-
4 LOOP_BW_SEL OUT0_SEL LMH1229: 4-level CDR loop bandwidth control.
LMH1297: Don't care. OUT0 always enabled in EQ mode.
For pin compatible functionality: Leave floating (Level F).
5 OUT_MUX_SEL EQ/CD_SEL LMH1229: 4-level output mux select control.
LMH1297: Tie low for EQ mode
For pin compatible functionality: Tie low for 100Ω OUT0 PCB output only.
9 VOD_DE HOST_EQ0 None
12 MODE_SEL MODE_SEL LMH1229: Level H forces Power save mode (SPI enabled).
LMH1297: Level H reserved.
For pin compatible functionality: Use Levels F, R, or L only.
14 SDI_OUT_SEL SDI_OUT_SEL None
15 LF+ RSV2 LMH1229: Optional external loop filter cap (do not connect for default operation).
LMH1297: Reserved (do not connect).
For pin compatible functionality: Leave floating.
16 LF- RSV3
17 OUT_CTRL OUT_CTRL LMH1229: Selects bypass mode operation for OUT0, OUT1, and SDI_OUT.
LMH1297: Selects bypass mode operation for OUT0 only
For pin compatible functionality: Leave floating (Level F).
24 SDI_VOD SDI_VOD None
27 LOCK_N LOCK_N None
32 ENABLE ENABLE None
11 CS_N_ADDR0 SS_N_ADDR0 None
Note: There are differences in LMH1229 vs. LMH1297 SMBus mode device addresses.
28 POCI_ADDR1 MISO_ADDR1 None
Note: There are differences in LMH1229 vs. LMH1297 SMBus mode device addresses.
13 PICO_SDA MOSI_SDA None
29 SCK_SCL SCK_SCL None
10 RSV1 RSV1 None
25 RSV2 RSV4 None
26 RSV3 RSV5 None
3, 6, 20 VSS VSS None
30 VIN VIN None
21 VIN VDD_CDR None. Connect to same supply as Pin 30 (VIN) externally.
(1) In the difference summary, LMH1297 is assumed to be operating in EQ mode.