Small gate capacitance and Miller capacitance enable enhancement mode GaN FETs to operate with fast switching speed. The induced high dv/dt and di/dt, coupled with a low gate threshold voltage and limited headroom of enhancement mode GaN FETs gate voltage, make the circuit layout crucial to the optimum performance. Following are some recommendations:
- Place the GaN FETs as close as possible to the gate driver. The main priority
of the layout is to decrease overall loop inductance and to minimize noise
coupling issues by confining the peak currents that charge and discharge the GaN
FET gates to a minimal physical area on the printed circuit board.
- Minimize the loop area of the bootstrap charging
path as it can contain high peak currents. Given that the TPS7H60x5 has multiple bootstrap
charging options, and that the charging takes place on a cycle-by-cycle basis, place both
the bootstrap capacitor and diode to facilitate a small loop area for the chosen charging
method.
- Place all bypass capacitors (VIN to AGND, BP5L to AGND, BP5H to ASW, BOOT to
ASW) as close to the device and respective pins as possible. Capacitors with
low ESR and ESL are recommended. If possible, place these capacitors on the
same side of the printed circuit board as the gate driver.
- Separate power traces and signal traces and minimize any overlap of the signals
on different printed circuit board layers.
- The parasitic inductance in series with the
source of the high-side FET and the low-side FET
can impose excessive negative voltage transients
on the driver during switching. Use short,
low-inductance paths to connect PSW to the
high-side FET source and PGND to the low-side FET
source.
- To prevent excessive ringing on the input power bus, good decoupling practices
are required by placing low-ESR capacitors adjacent to the GaN FETs.