SNOU179A May   2021  – September 2021 LM74501-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Setup
    1. 2.1 I/O Connector Description
    2. 2.2 Board Setup
    3. 2.3 Schematic
  4. 3Operation
    1. 3.1 LM74501-Q1EVM Performance Capture
      1. 3.1.1 LM74501-Q1EVM Startup
      2. 3.1.2 Startup Reverse Polarity (–12 V)
  5. 4EVM Board Assembly Drawings and Layout Guidelines
    1. 4.1 PCB Drawings
    2. 4.2 Bill of Materials
  6. 5Revision History

2.1 I/O Connector Description

    VINJ1: Power input connector to the positive rail of the input power supply
    GND1J3: Ground connection for the power supply
    VOUTJ2: Power output connector to the positive side of the load
    GND2J4: Ground connection for the load
    ENJ5: Jumper to enable LM74501Q1 gate driver
    1-2 position connects EN to Source, 2-3 position connects EN to GND
    Test PointsVINA, VOUTA,GATE,ENA,BATT_MON, GND1, and GND2 are test points
GUID-20200910-CA0I-VWFM-FKMX-K0HVM2Z1DBKG-low.gifFigure 2-1 LM74501-Q1EVM Typical Application Circuit