SNVSCC2I November   2022  – August 2026 TPS389C03-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I2C
      2. 7.3.2  Maskable Interrupt (AMSK)
      3. 7.3.3  VDD
      4. 7.3.4  MON
      5. 7.3.5  NRST
      6. 7.3.6  NIRQ
      7. 7.3.7  ADC
      8. 7.3.8  Packet Error Checking (PEC)
      9. 7.3.9  Q&A Watchdog
        1. 7.3.9.1 Question and Token Generation
        2. 7.3.9.2 Q&A Watchdog Open and Close Window Delay
        3. 7.3.9.3 Q&A Watchdog Status Register
        4. 7.3.9.4 Q&A Watchdog Timing
        5. 7.3.9.5 Q&A Watchdog State Machine and Test Program
      10. 7.3.10 Error Signal Monitoring (ESM)
        1. 7.3.10.1 ESM Timing
      11. 7.3.11 Register Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS389C03-Q1 Power ON
  9. 8 Register Maps
    1. 8.1 Registers Overview
      1. 8.1.1 BANK0 Registers
      2. 8.1.2 BANK1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supply Guidelines
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Documentation Support
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.1.2 BANK1 Registers

Table 8-26 lists the memory-mapped registers for the BANK1 registers. All register offset addresses not listed in Table 8-26 should be considered as reserved locations and the register contents should not be modified.

Table 8-26 BANK1 Registers
OffsetAcronymRegister NameSection
10hVMON_CTLVMON device control register.Section 8.1.2.1
11hVMON_MISCMiscellaneous VMON configurations.Section 8.1.2.2
12hTEST_CFGBuilt-In Self Test (BIST) execution configuration.Section 8.1.2.3
13hIEN_UVHFHigh Frequency channel Under-Voltage Interrupt Enable registerSection 8.1.2.4
14hIEN_UVLFLow Frequency channel Under-Voltage Interrupt Enable register.Section 8.1.2.5
15hIEN_OVHFHigh Frequency channel Over-Voltage Interrupt Enable register.Section 8.1.2.6
16hIEN_OVLFLow Frequency channel Over-Voltage Interrupt Enable register.Section 8.1.2.7
1BhIEN_CONTROLControl and Communication Fault Interrupt Enable register.Section 8.1.2.8
1ChIEN_TESTInternal Test and Configuration Load Fault Interrupt Enable registerSection 8.1.2.9
1DhIEN_VENDORVendor Specific Internal Interrupt Enable register.Section 8.1.2.10
1EhMON_CH_ENChannel Voltage Monitoring Enable.Section 8.1.2.11
1FhVRANGE_MULTChannel Voltage Monitoring Range/Scaling.Section 8.1.2.12
30hUV_HF[2]Channel 2 High Frequency channel Under-Voltage threshold.Section 8.1.2.13
31hOV_HF[2]Channel 2 High Frequency channel Over-Voltage threshold.Section 8.1.2.14
32hUV_LF[2]Channel 2 Low Frequency channel Under-Voltage threshold.Section 8.1.2.15
33hOV_LF[2]Channel 2 Low Frequency channel Over-Voltage threshold.Section 8.1.2.16
34hFLT_HF[2]Channel 2 UV and OV debouncing for High Frequency thresholds comparator output.Section 8.1.2.17
35hFC_LF[2]Channel 2 Low Frequency Path G(s) Cutoff Frequency (-3dB point). The register changes the filter properties of the programmable LPF such that the total frequency response G(s) meets these cutoff frequencies.Section 8.1.2.18
40hUV_HF[3]Channel 3 High Frequency channel Under-Voltage threshold.Section 8.1.2.19
41hOV_HF[3]Channel 3 High Frequency channel Over-Voltage threshold.Section 8.1.2.20
42hUV_LF[3]Channel 3 Low Frequency channel Under-Voltage threshold.Section 8.1.2.21
43hOV_LF[3]Channel 3 Low Frequency channel Over-Voltage threshold.Section 8.1.2.22
44hFLT_HF[3]Channel 3 UV and OV debouncing for High Frequency thresholds comparator output.Section 8.1.2.23
45hFC_LF[3]Channel 3 Low Frequency Path G(s) Cutoff Frequency (-3dB point). The register changes the filter properties of the programmable LPF such that the total frequency response G(s) meets these cutoff frequencies.Section 8.1.2.24
50hUV_HF[4]Channel 4 High Frequency channel Under-Voltage threshold.Section 8.1.2.25
51hOV_HF[4]Channel 4 High Frequency channel Over-Voltage threshold.Section 8.1.2.26
52hUV_LF[4]Channel 4 Low Frequency channel Under-Voltage threshold.Section 8.1.2.27
53hOV_LF[4]Channel 4 Low Frequency channel Over-Voltage threshold.Section 8.1.2.28
54hFLT_HF[4]Channel 4 UV and OV debouncing for High Frequency thresholds comparator output.Section 8.1.2.29
55hFC_LF[4]Channel 4 Low Frequency Path G(s) Cutoff Frequency (-3dB point). The register changes the filter properties of the programmable LPF such that the total frequency response G(s) meets these cutoff frequencies.Section 8.1.2.30
9EhESMESM threshold time for asserting a fault.Section 8.1.2.31
9FhTI_CONTROLManual BIST/WD EN/Manual Reset via I2C/ESM deglitch/Reset delaySection 8.1.2.32
A1hAMSK_ONAuto-mask UVLF, UVHF, and OVHF interrupts on power up transitions.Section 8.1.2.33
A2hAMSK_OFFAuto-mask UVLF, UVHF, and OVHF interrupts on power down transitions.Section 8.1.2.34
A5hSEQ_TOUT_MSBTimeout for UV faults during powerup and power down.Section 8.1.2.35
A6hSEQ_TOUT_LSBTimeout for UV faults during powerup and power down.Section 8.1.2.36
A8hSEQ_UP_THLDThreshold at which AMSK is released (VMON considered on) for power up.Section 8.1.2.37
A9hSEQ_DN_THLDThreshold at which AMSK is released (VMON considered off) for power down.Section 8.1.2.38
AAhWDT_CFGMax violation count for WD and Delay multiplier for Start Up Window.Section 8.1.2.39
ABhWDT_CLOSEClose Window Time.Section 8.1.2.40
AChWDT_OPENOpen Window Time.Section 8.1.2.41
ADhWDT_QA_CFGFeedback/Poly/Seed for Watchdog.Section 8.1.2.42
AEhWDT_ANSWERAnswer for the Watchdog.Section 8.1.2.43
F0hBANK_SELBank Select.Section 8.1.2.44

Complex bit access types are encoded to fit into small table cells. Table 8-27 shows the codes that are used for access types in this section.

Table 8-27 BANK1 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.1.2.1 VMON_CTL Register (Offset = 10h) [Reset = 20h]

VMON_CTL is shown in Table 8-28.

Return to the Summary Table.

VMON device control register.

Table 8-28 VMON_CTL Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W0h Reserved
4FORCE_WDO_LOWR/W0h Force assertion of WDO
3RESET_PROTR/W0h Reset_Prot = read 0, write 1 to clear Protection registers
2-1RESERVEDR/W0h Reserved
0FORCE_NIRQ_LOWR/W0h Force assertion of NIRQ

8.1.2.2 VMON_MISC Register (Offset = 11h) [Reset = X0h]

VMON_MISC is shown in Table 8-29.

Return to the Summary Table.

Miscellaneous VMON configurations.

Table 8-29 VMON_MISC Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0h Reserved
6-4WDO_DLY[2:0]R/W0h WDO_Delay (not applicable for latched WDO)
3-2RESERVEDR/W0h Reserved
1REQ_PECR/WXh Require PEC.
0 = PEC not required
1 = PEC required
0EN_PECR/WXh Enable PEC.
0 = PEC not enabled
1 = PEC enabled

8.1.2.3 TEST_CFG Register (Offset = 12h) [Reset = X0h]

TEST_CFG is shown in Table 8-30.

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Built-In Self Test (BIST) execution configuration.

Table 8-30 TEST_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR/W0h Reserved
2AT_SHDNR/WXh Run BIST at SHDN
1AT_POR[1]R/WXh Run BIST at POR, 2nd bit for redundancy
0AT_POR[0]R/WXh Run BIST at POR

8.1.2.4 IEN_UVHF Register (Offset = 13h) [Reset = X0h]

IEN_UVHF is shown in Table 8-31.

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High Frequency channel Under-Voltage Interrupt Enable register

Table 8-31 IEN_UVHF Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h Reserved
3MON[4]R/WXh UVHF interrupt enable for MON4,
0 = Disable,
1 = Enable
2MON[3]R/WXh UVHF interrupt enable for MON3,
0 = Disable,
1 = Enable
1MON[2]R/WXh UVHF interrupt enable for MON2,
0 = Disable,
1 = Enable
0RESERVEDR/W0h Reserved

8.1.2.5 IEN_UVLF Register (Offset = 14h) [Reset = X0h]

IEN_UVLF is shown in Table 8-32.

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Low Frequency channel Under-Voltage Interrupt Enable register.

Table 8-32 IEN_UVLF Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h Reserved
3MON[4]R/WXh UVLF interrupt enable for MON4,
0 = Disable,
1 = Enable
2MON[3]R/WXh UVLF interrupt enable for MON3,
0 = Disable,
1 = Enable
1MON[2]R/WXh UVLF interrupt enable for MON2,
0 = Disable,
1 = Enable
0RESERVEDR/W0h Reserved

8.1.2.6 IEN_OVHF Register (Offset = 15h) [Reset = X0h]

IEN_OVHF is shown in Table 8-33.

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High Frequency channel Over-Voltage Interrupt Enable register.

Table 8-33 IEN_OVHF Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h Reserved
3MON[4]R/WXh OVHF interrupt enable for MON4,
0 = Disable,
1 = Enable
2MON[3]R/WXh OVHF interrupt enable for MON3,
0 = Disable,
1 = Enable
1MON[2]R/WXh OVHF interrupt enable for MON2,
0 = Disable,
1 = Enable
0RESERVEDR/W0h Reserved

8.1.2.7 IEN_OVLF Register (Offset = 16h) [Reset = X0h]

IEN_OVLF is shown in Table 8-34.

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Low Frequency channel Over-Voltage Interrupt Enable register.

Table 8-34 IEN_OVLF Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h Reserved
3MON[4]R/WXh OVLF interrupt enable for MON4,
0 = Disable,
1 = Enable
2MON[3]R/WXh OVLF interrupt enable for MON3,
0 = Disable,
1 = Enable
1MON[2]R/WXh OVLF interrupt enable for MON2,
0 = Disable,
1 = Enable
0RESERVEDR/W0h Reserved

8.1.2.8 IEN_CONTROL Register (Offset = 1Bh) [Reset = X0h]

IEN_CONTROL is shown in Table 8-35.

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Control and Communication Fault Interrupt Enable register.

Table 8-35 IEN_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W0h Reserved
4RT_CRC_IntR/W0h Register Run time CRC (Cyclic Redundancy Checking) error Interrupt is a static CRC performed on the register map content. If enabled there does not need to be any data read or write for this CRC check to occur. The purpose of this CRC is to identify if a static bit flip or random error in the register map content has occurred. This safety mechanism is carried out using a CRC-8 polynomial, in the case of a read or write operation the register map content will change and the polynomial is re-calculated with the new value after the changes. Interrupt is reported in INT_CONTROL_F_CRC register of Bank 0.
0 = Disable Interrupt Mapping,
1 = Enable Interrupt Mapping
3RESERVEDR/W0h Reserved
2TSD_INTR/WXh Thermal shutdown Interrupt.
0 = Disable,
1 = Enable
1RESERVEDR/W0h Reserved
0PEC_INTR/WXh PEC Error Interrupt.
0 = Disable,
1 = Enable

8.1.2.9 IEN_TEST Register (Offset = 1Ch) [Reset = X0h]

IEN_TEST is shown in Table 8-36.

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Internal Test and Configuration Load Fault Interrupt Enable register

Table 8-36 IEN_TEST Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h Reserved
3ECC_SECR/WXh SEC Error Interrupt.
0 = Disable,
1 = Enable
2RESERVEDR/W0h Reserved
1BIST_Complete_INTR/WXh BIST complete Interrupt.
0 = Disable,
1 = Enable
0BIST_Fail_INTR/WXh BIST Fail Interrupt.
0 = Disable,
Enable = 1

8.1.2.10 IEN_VENDOR Register (Offset = 1Dh) [Reset = X0h]

IEN_VENDOR is shown in Table 8-37.

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Vendor Specific Internal Interrupt Enable register.

Table 8-37 IEN_VENDOR Register Field Descriptions
BitFieldTypeResetDescription
7Startup Self-Test_CRCR/W0h Startup Self-Test_CRC Interrupt.
0 = Disable Interrupt Mapping,
1 = Enable Interrupt Mapping
6RESERVEDR/W0h Reserved
5NRST_MISMATCHR/W0h NRST mismatch Interrupt.
0 = Disable Interrupt Mapping,
1 = Enable Interrupt Mapping
4ESM_TO_WDOR/W0h Maps ESM fault to WDO.
0 = Not mapped
1 = Mapped
3ESM_TO_NIRQR/WXh Maps ESM fault to NIRQ.
0 = Not mapped
1 = Mapped
2WDT_TO_NIRQR/WXh Maps Watchdog fault to NIRQ.
0 = Not mapped
1 = Mapped
1ESM_TO_NRSTR/WXh Maps ESM fault to NRST.
0 = Not mapped
1 = Mapped
0WDT_TO_NRSTR/WXh Maps Watchdog fault to NRST.
0 = Not mapped
1 = Mapped

8.1.2.11 MON_CH_EN Register (Offset = 1Eh) [Reset = X0h]

MON_CH_EN is shown in Table 8-38.

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Channel Voltage Monitoring Enable.

Table 8-38 MON_CH_EN Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h Reserved
3MON[4]R/WXh Enables MON4 monitoring.
0 = Disabled,
1 = Enabled
2MON[3]R/WXh Enables MON3 monitoring.
0 = Disabled,
1 = Enabled
1MON[2]R/WXh Enables MON2 monitoring.
0 = Disabled,
1 = Enabled
0RESERVEDR/W0h Reserved

8.1.2.12 VRANGE_MULT Register (Offset = 1Fh) [Reset = X0h]

VRANGE_MULT is shown in Table 8-39.

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Channel Voltage Monitoring Range/Scaling.

Table 8-39 VRANGE_MULT Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h Reserved
3MON[4]R/WXh Scalar for MON4.
0 = 1x,
1 = 4x
2MON[3]R/WXh Scalar for MON3.
0 = 1x,
1 = 4x
1MON[2]R/WXh Scalar for MON2.
0 = 1x,
1 = 4x
0RESERVEDR/W0h Reserved

8.1.2.13 UV_HF[2] Register (Offset = 30h) [Reset = X0h]

UV_HF[2] is shown in Table 8-40.

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Channel 2 High Frequency channel Under-Voltage threshold.

Table 8-40 UV_HF[2] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V
with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

8.1.2.14 OV_HF[2] Register (Offset = 31h) [Reset = X0h]

OV_HF[2] is shown in Table 8-41.

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Channel 2 High Frequency channel Over-Voltage threshold.

Table 8-41 OV_HF[2] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V
with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

8.1.2.15 UV_LF[2] Register (Offset = 32h) [Reset = X0h]

UV_LF[2] is shown in Table 8-42.

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Channel 2 Low Frequency channel Under-Voltage threshold.

Table 8-42 UV_LF[2] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Undervoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V
with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

8.1.2.16 OV_LF[2] Register (Offset = 33h) [Reset = X0h]

OV_LF[2] is shown in Table 8-43.

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Channel 2 Low Frequency channel Over-Voltage threshold.

Table 8-43 OV_LF[2] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Overvoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V
with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

8.1.2.17 FLT_HF[2] Register (Offset = 34h) [Reset = X0h]

FLT_HF[2] is shown in Table 8-44.

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Channel 2 UV and OV debouncing for High Frequency thresholds comparator output.

Table 8-44 FLT_HF[2] Register Field Descriptions
BitFieldTypeResetDescription
7-4OV_DEB[3:0]R/W0h Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs
3-0UV_DEB[3:0]R/WXh Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs

8.1.2.18 FC_LF[2] Register (Offset = 35h) [Reset = X0h]

FC_LF[2] is shown in Table 8-45.

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Channel 2 Low Frequency Path G(s) Cutoff Frequency (-3dB point). The register changes the filter properties of the programmable LPF such that the total frequency response G(s) meets these cutoff frequencies.

Table 8-45 FC_LF[2] Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W0h Reserved
4OVHF_TO_NRSTR/W0h Maps MON2 OVHF fault to NRST
0 = Not mapped,
1 = Mapped
3UVHF_TO_NRSTR/WXh Maps MON2 UVHF fault to NRST
0 = Not mapped,
1 = Mapped
2-0Cut_off_Freq[2:0]R/WXh MON2 Cut of frequency for LF faults filter
000 = Invalid
001 = Invalid
010 = 250Hz
011 = 500Hz
100 = 1kHz
101 = 2kHz
110 = 4kHz
111 = Invalid

8.1.2.19 UV_HF[3] Register (Offset = 40h) [Reset = X0h]

UV_HF[3] is shown in Table 8-46.

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Channel 3 High Frequency channel Under-Voltage threshold.

Table 8-46 UV_HF[3] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V
with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8Vto 5.9V with 1 LSB = 20mV.

8.1.2.20 OV_HF[3] Register (Offset = 41h) [Reset = X0h]

OV_HF[3] is shown in Table 8-47.

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Channel 3 High Frequency channel Over-Voltage threshold.

Table 8-47 OV_HF[3] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V
with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

8.1.2.21 UV_LF[3] Register (Offset = 42h) [Reset = X0h]

UV_LF[3] is shown in Table 8-48.

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Channel 3 Low Frequency channel Under-Voltage threshold.

Table 8-48 UV_LF[3] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Undervoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V
with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

8.1.2.22 OV_LF[3] Register (Offset = 43h) [Reset = X0h]

OV_LF[3] is shown in Table 8-49.

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Channel 3 Low Frequency channel Over-Voltage threshold.

Table 8-49 OV_LF[3] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Overvoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V
with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

8.1.2.23 FLT_HF[3] Register (Offset = 44h) [Reset = X0h]

FLT_HF[3] is shown in Table 8-50.

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Channel 3 UV and OV debouncing for High Frequency thresholds comparator output.

Table 8-50 FLT_HF[3] Register Field Descriptions
BitFieldTypeResetDescription
7-4OV_DEB[3:0]R/W0h Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs
3-0UV_DEB[3:0]R/WXh Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs

8.1.2.24 FC_LF[3] Register (Offset = 45h) [Reset = X0h]

FC_LF[3] is shown in Table 8-51.

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Channel 3 Low Frequency Path G(s) Cutoff Frequency (-3dB point). The register changes the filter properties of the programmable LPF such that the total frequency response G(s) meets these cutoff frequencies.

Table 8-51 FC_LF[3] Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W0h Reserved
4OVHF_TO_NRSTR/W0h Maps MON3 OVHF fault to NRST
0 = Not mapped,
1 = Mapped
3UVHF_TO_NRSTR/WXh Maps MON3 UVHF fault to NRST
0 = Not mapped,
1 = Mapped
2-0Cut_off_Freq[2:0]R/WXh MON3 Cut of frequency for LF faults filter
000 = Invalid
001 = Invalid
010 = 250Hz
011 = 500Hz
100 = 1kHz
101 = 2kHz
110 = 4kHz
111 = Invalid

8.1.2.25 UV_HF[4] Register (Offset = 50h) [Reset = X0h]

UV_HF[4] is shown in Table 8-52.

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Channel 4 High Frequency channel Under-Voltage threshold.

Table 8-52 UV_HF[4] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V
with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

8.1.2.26 OV_HF[4] Register (Offset = 51h) [Reset = X0h]

OV_HF[4] is shown in Table 8-53.

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Channel 4 High Frequency channel Over-Voltage threshold.

Table 8-53 OV_HF[4] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V
with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

8.1.2.27 UV_LF[4] Register (Offset = 52h) [Reset = X0h]

UV_LF[4] is shown in Table 8-54.

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Channel 4 Low Frequency channel Under-Voltage threshold.

Table 8-54 UV_LF[4] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Undervoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V
with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

8.1.2.28 OV_LF[4] Register (Offset = 53h) [Reset = X0h]

OV_LF[4] is shown in Table 8-55.

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Channel 4 Low Frequency channel Over-Voltage threshold.

Table 8-55 OV_LF[4] Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Overvoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V
with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

8.1.2.29 FLT_HF[4] Register (Offset = 54h) [Reset = X0h]

FLT_HF[4] is shown in Table 8-56.

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Channel 4 UV and OV debouncing for High Frequency thresholds comparator output.

Table 8-56 FLT_HF[4] Register Field Descriptions
BitFieldTypeResetDescription
7-4OV_DEB[3:0]R/W0h Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs
3-0UV_DEB[3:0]R/WXh Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs
0001b = 0.2µs 1001b = 51.2µs
0010b = 0.4µs 1010b = 102.4µs
0011b = 0.8µs 1011b = 102.4µs
0100b = 1.6µs 1100b = 102.4µs
0101b = 3.2µs 1101b = 102.4µs
0110b = 6.4µs 1110b = 102.4µs
0111b = 12.8µs 1111b = 102.4µs

8.1.2.30 FC_LF[4] Register (Offset = 55h) [Reset = X0h]

FC_LF[4] is shown in Table 8-57.

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Channel 4 Low Frequency Path G(s) Cutoff Frequency (-3dB point). The register changes the filter properties of the programmable LPF such that the total frequency response G(s) meets these cutoff frequencies.

Table 8-57 FC_LF[4] Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W0h Reserved
4OVHF_TO_NRSTR/W0h Maps MON4 OVHF fault to NRST
0 = Not mapped,
1 = Mapped
3UVHF_TO_NRSTR/WXh Maps MON4 UVHF fault to NRST
0 = Not mapped,
1 = Mapped
2-0Cut_off_Freq[2:0]R/WXh MON4 Cut of frequency for LF faults filter
000 = Invalid
001 = Invalid
010 = 250Hz
011 = 500Hz
100 = 1kHz
101 = 2kHz
110 = 4kHz
111 = Invalid

8.1.2.31 ESM Register (Offset = 9Eh) [Reset = X0h]

ESM is shown in Table 8-58.

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ESM threshold time for asserting a fault.

Table 8-58 ESM Register Field Descriptions
BitFieldTypeResetDescription
7-0THRESHOLD[7:0]R/WXh Threshold value representing the ESM delay time (1ms to 864ms)

8.1.2.32 TI_CONTROL Register (Offset = 9Fh) [Reset = X0h]

TI_CONTROL is shown in Table 8-59.

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Manual BIST/WD EN/Manual Reset via I2C/ESM deglitch/Reset delay

Table 8-59 TI_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
7ENTER_BISTR/W0h Manual BIST.
1 = Enter BIST
6WDT_ENR/W0h Watchdog EN to be used along with hardware WD_EN pin.
1 = Watchdog Enabled,
0 = Watchdog Disabled
5I2C_MRR/W0h Manual Reset.
1 = Assert NRST low
4-3ESM_DEB[1:0]R/WXh ESM debounce filter
00 = 10µs
01 = 25µs
10 = 50µs
11 = 100µs
2-0RST_DLY[2:0]R/WXh Reset delay
000 = 200µs
001 = 1ms
010 = 10ms
011 = 16ms
100 = 20ms
101 = 70ms
110 = 100ms
111 = 200ms

8.1.2.33 AMSK_ON Register (Offset = A1h) [Reset = X0h]

AMSK_ON is shown in Table 8-60.

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Auto-mask UVLF, UVHF, and OVHF interrupts on power up transitions.

Table 8-60 AMSK_ON Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h Reserved
3MON[4]R/WXh Automask at power on for MON4.
0 = Disabled
1 = Enabled
2MON[3]R/WXh Automask at power on for MON3.
0 = Disabled
1 = Enabled
1MON[2]R/WXh Automask at power on for MON2.
0 = Disabled
1 = Enabled
0RESERVEDR/W0h Reserved

8.1.2.34 AMSK_OFF Register (Offset = A2h) [Reset = X0h]

AMSK_OFF is shown in Table 8-61.

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Auto-mask UVLF, UVHF, and OVHF interrupts on power down transitions.

Table 8-61 AMSK_OFF Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h Reserved
3MON[4]R/WXh Automask at power off for MON4.
0 = Disabled
1 = Enabled
2MON[3]R/WXh Automask at power off for MON3.
0 = Disabled
1 = Enabled
1MON[2]R/WXh Automask at power off for MON2.
0 = Disabled
1 = Enabled
0RESERVEDR/W0h Reserved

8.1.2.35 SEQ_TOUT_MSB Register (Offset = A5h) [Reset = X0h]

SEQ_TOUT_MSB is shown in Table 8-62.

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Timeout for UV faults during powerup and power down.

Table 8-62 SEQ_TOUT_MSB Register Field Descriptions
BitFieldTypeResetDescription
7-0MILLISEC[15:8]R/WXh Sequence time out MSB

8.1.2.36 SEQ_TOUT_LSB Register (Offset = A6h) [Reset = X0h]

SEQ_TOUT_LSB is shown in Table 8-63.

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Timeout for UV faults during powerup and power down.

Table 8-63 SEQ_TOUT_LSB Register Field Descriptions
BitFieldTypeResetDescription
7-0MILLISEC[7:0]R/WXh Sequence time out LSB

8.1.2.37 SEQ_UP_THLD Register (Offset = A8h) [Reset = X0h]

SEQ_UP_THLD is shown in Table 8-64.

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Threshold at which AMSK is released (VMON considered on) for power up.

Table 8-64 SEQ_UP_THLD Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h Reserved
3MON[4]R/WXh AMSK releases at UVLF or OFF threshold for MON4.
0 = off threshold,
1 = UVLF threshold
2MON[3]R/WXh AMSK releases at UVLF or OFF threshold for MON3.
0 = off threshold,
1 = UVLF threshold
1MON[2]R/WXh AMSK releases at UVLF or OFF threshold for MON2.
0 = off threshold,
1 = UVLF threshold
0RESERVEDR/W0h Reserved

8.1.2.38 SEQ_DN_THLD Register (Offset = A9h) [Reset = X0h]

SEQ_DN_THLD is shown in Table 8-65.

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Threshold at which AMSK is released (VMON considered off) for power down.

Table 8-65 SEQ_DN_THLD Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h Reserved
3MON[4]R/WXh AMSK releases at UVLF or OFF threshold for MON4.
0 = off threshold,
1 = UVLF threshold
2MON[3]R/WXh AMSK releases at UVLF or OFF threshold for MON3.
0 = off threshold,
1 = UVLF threshold
1MON[2]R/WXh AMSK releases at UVLF or OFF threshold for MON2.
0 = off threshold,
1 = UVLF threshold
0RESERVEDR/W0h Reserved

8.1.2.39 WDT_CFG Register (Offset = AAh) [Reset = X0h]

WDT_CFG is shown in Table 8-66.

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Max violation count for WD and Delay multiplier for Start Up Window.

Table 8-66 WDT_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0h Reserved
6-4MAX_VIOLATION_COUNTR/W0h Max violation count for Watchdog
000 = 0
001 = 1
010 = 2
011 = 3
100 = 4
101 = 5
110 = 6
111 = 7
3RESERVEDR/W0h Reserved
2-0WDT_Startup_DLY_MULTIPLIER[2:0]R/WXh Watchdog Startup delay multiplier
000 = 0
001 = 1
010 = 2
011 = 3
100 = 4
101 = 5
110 = 6
111 = 7

8.1.2.40 WDT_CLOSE Register (Offset = ABh) [Reset = X0h]

WDT_CLOSE is shown in Table 8-67.

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Close Window Time.

Table 8-67 WDT_CLOSE Register Field Descriptions
BitFieldTypeResetDescription
7-0CLOSE[7:0]R/WXh Close window time (1ms to 864ms)

8.1.2.41 WDT_OPEN Register (Offset = ACh) [Reset = X0h]

WDT_OPEN is shown in Table 8-68.

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Open Window Time.

Table 8-68 WDT_OPEN Register Field Descriptions
BitFieldTypeResetDescription
7-0OPEN[7:0]R/WXh Open window time (1ms to 864ms)

8.1.2.42 WDT_QA_CFG Register (Offset = ADh) [Reset = 00h]

WDT_QA_CFG is shown in Table 8-69.

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FeedbackPolt/Seed for Watchdog.

Table 8-69 WDT_QA_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-6FDBK[1:0]R/W0h Feedback used for computing answer
5-4POLY[1:0]R/W0h Poly used for computing answer
3-0SEED[3:0]R/W0h Seed used for computing answer

8.1.2.43 WDT_ANSWER Register (Offset = AEh) [Reset = 00h]

WDT_ANSWER is shown in Table 8-70.

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Answer for the Watchdog.

Table 8-70 WDT_ANSWER Register Field Descriptions
BitFieldTypeResetDescription
7-0ANSWER[7:0]R/W0h Answer

8.1.2.44 BANK_SEL Register (Offset = F0h) [Reset = 00h]

BANK_SEL is shown in Table 8-71.

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Bank Select.

Table 8-71 BANK_SEL Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0h Reserved
0BANK_SelectR/W0h Represents bank selection.
0 = Bank 0
1 = Bank 1