SNVSCH9 April   2025 TPS388C0-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
      1. 7.3.1 TPS388C0x-Q1 Power ON
      2. 7.3.2 Built-In Self Test and Configuration Load
        1. 7.3.2.1 Notes on BIST Execution
      3. 7.3.3 General Monitoring
        1. 7.3.3.1 ACTIVE Monitoring
    4. 7.4 Feature Description
      1. 7.4.1 VDD
      2. 7.4.2 Maskable Interrupt (AMSK)
      3. 7.4.3 MON
      4. 7.4.4 NRST
      5. 7.4.5 NIRQ
      6. 7.4.6 I2C
      7. 7.4.7 Packet Error Checking (PEC)
      8. 7.4.8 Window Watchdog
      9. 7.4.9 Window Watchdog Timer
    5. 7.5 Register Maps
      1. 7.5.1 Registers Overview
        1. 7.5.1.1 BANK0 Registers
        2. 7.5.1.2 BANK1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Automotive Multichannel Sequencer and Monitor
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Guidelines
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Documentation Support
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

9.1 Device Nomenclature

Table 9-1 and Table 9-2 show how to decode the function of the device based on the part number.

Table 9-1 Device Thresholds TPS388C06-Q1
ORDERING CODE Thresholds VMON2 (V) VMON3 (V) VMON4 (V) VMON5 (V) VMON6 (V) VMON7 (V)

TPS388C06001RTER-Q1

 UV_HF/OV_HF

3.0/3.6

1.08/1.30

1.60/1.98

0.90/1.1

1.60/1.98

2.72/3.6
Table 9-2 Device Configuration Table
ORDERING CODE WD Close/Open Windows SCALING OV/UV DEBOUNCE NRST mapping WD Fault mapping BIST SEQ TIMEOUT/RESET DELAY PEC(1) I2C PULL-UP VOLTAGE (V)

WD Violation count/WD startup multiplier

TPS388C06001RTER

 10ms/188ms

4/4/4/4/4/4

 102.4μsec MON7 NIRQ at POR 25ms/20ms Disable 3.3

1/0
(1) For parts with PEC enabled:
  1. PEC calculation is based on initializing to 0x00.
  2. In case of a PEC violation there needs to be a subsequent I2C transaction before NIRQ is asserted.
  3. If incorrect PEC is given TPS388C0x-Q1 asserts NIRQ.
  4. If there is an extra byte after successfully writing the correct PEC byte, NIRQ asserts and the write fails.