SNVSCU7A July   2025  – August 2026 LM65460-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1  Output Voltage Selection
      2. 7.3.2  EN Pin and Use as VIN UVLO
      3. 7.3.3  Mode Selection
        1. 7.3.3.1 MODE/SYNC Pin Uses for Synchronization
        2. 7.3.3.2 Clock Locking
      4. 7.3.4  Adjustable Switching Frequency
      5. 7.3.5  Dual Phase Operation
      6. 7.3.6  Dual Randrom Spread Spectrum (DRSS)
      7. 7.3.7  Internal LDO, VCC UVLO, and BIAS Input
      8. 7.3.8  Bootstrap Voltage (BST Pin)
      9. 7.3.9  Soft Start and Recovery From Dropout
      10. 7.3.10 Safety Features
        1. 7.3.10.1 Power-Good Monitor
        2. 7.3.10.2 Overcurrent and Short-Circuit Protection
        3. 7.3.10.3 Hiccup
        4. 7.3.10.4 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Peak Current Mode Operation
        2. 7.4.2.2 Auto Mode Operation
          1. 7.4.2.2.1 Diode Emulation
        3. 7.4.2.3 FPWM Mode Operation
        4. 7.4.2.4 Dropout
        5. 7.4.2.5 Recovery from Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Choosing the Switching Frequency
        3. 8.2.2.3 FB for Adjustable or Fixed Output Voltage Mode
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Output Capacitor Selection
        6. 8.2.2.6 Input Capacitor Selection
        7. 8.2.2.7 CBOOT
        8. 8.2.2.8 External UVLO
        9. 8.2.2.9 Maximum Ambient Temperature
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground and Thermal Considerations
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 13.5V, VEN = VIN, VOUT = 3.3V, fSW = 2.2MHz
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY (VIN PIN)
VINUVLO_R VIN UVLO rising threshold VIN rising (needed to start up), IVCC = 0A 3.2 3.4 3.7 V
VINUVLO_F VIN UVLO falling threshold VIN falling (after operating), IVCC = 0A 2.5 2.55 V
VINUVLO_H VIN UVLO hysteresis 0.9 V
IVIN VIN pin input current, internal COMP, no switching  VBIAS = 3.3V + 2% 1.0 µA
IBIAS(FIX-3.3V) BIAS pin input current, fixed 3.3V output, no switching VBIAS = 3.3V + 2%, Auto Mode enabled 10 µA
IQ(FIX-3.3V) Total VIN quiescent current, fixed 3.3V output, no switching VIN = 13.5V, VBIAS = 3.3V + 2%, TJ = 25℃, Auto Mode enabled 3.5 4 µA
TJ = 125℃  15 µA
IBIAS(ADJ-3.3V) BIAS pin input current, adjustable 3.3V output, no switching VFB = 0.8V + 2%, Auto Mode 8.6 µA
IQ(ADJ-3.3V) Total VIN quiescent current, adjustable 3.3V output, no switching VIN = 13.5V, VFB = 0.8V + 2%, Auto Mode 3.0 µA
IQ-SD VIN Shutdown supply current VEN = 0V, TJ = 25℃ 2 µA
ENABLE (EN PIN)
VEN_TH_R Enable voltage rising threshold VEN rising 1.15 1.25 1.35 V
VEN_TH_F Enable input low threshold VEN falling 0.9 1 1.11 V
VEN_HYS Enable voltage hysteresis 275 mV
IEN_LKG Enable input leakage current VEN = VIN 0.27 1.25 µA
INTERNAL LDO (VCC PIN)
VVCC Internal LDO output voltage 3.4V ≤ VIN ≤ 36V, VBIAS = 0V 3.35 V
3.4V ≤ VBIAS ≤ 30V 3.35 V
VVCC-UVLO_R VCC UVLO rising threshold VCC rising undervoltage threshold, IVCC = 0A 3.1 3.4 3.6 V
V VCC-UVLO_H VCC UVLO hysteresis Hysteresis below VVCC-UVLO_R, 0.9 1.31 V
VVCC-OVLO(R) VCC OVLO rising threshold VCC overvoltage rising threshold, IVCC = 0 A  4.38 V
VVCC-OVLO(F) VCC OVLO falling threshold VCC overvoltage falling threshold, IVCC = 0 A  3.63 V
tVCC-OVLO_DEGLITCH(R) VCC OVLO rising edge comparator delay 20 us
VOLTAGE REFERENCE (FB PIN)
VFB Internal feedback reference voltage FPWM Mode 0.792 0.8 0.808 V
IFB-LKG Feedback pin input leakage current VFB = 0.8V, adjustable Version 1.8 nA
FIXED OUTPUT VOLTAGE (BIAS PIN)
VOUT(3.3V) 3.3V fixed output voltage FB shorted to GND 3.25 3.3 3.35 V
VOUT(5V) 5.0V fixed output voltage FB shorted to VCC 4.92 5 5.065 V
STARTUP (SS PIN)
tEN_HIGH Enable HIGH to start of switching delay VFB = VRT = VMODE = GND,  VBIAS = VOUT 1.6 ms
tSS Internal fixed soft-start time Time from first SW pulse to VREF at 90% of set point 1.8 3.0 4.2 ms
gm(EXTERNAL) EA transconductance – external COMP VCOMP = 0.8V, VFB = +5% & VFB = -5% 1000 µS
VCOMP-EXT(h-clamp) COMP clamp voltage VFB = 0V, Adjustable Output voltage setting. Simulation only 1.2 V
CURRENT LIMITS AND HICCUP
IHS-LIM High side peak current limit, LM6X480-Q1 Duty-cycle approaches 0%. 11.9 13.6 15.3 A
ILS-LIM Low side valley current limit, LM6X480-Q1 Valley current limit on LS FET 9.4 10.8 12.2 A
IL-PEAK-MIN Minimum peak inductor current at minimum duty cycle, LM6X480-Q1 VVCC = 3.3V, tpulse ≤ 100ns, Auto Mode 2.7 A
IL-PEAK-MAX Minimum peak inductor current at maximum duty cycle, LM6X480Q1 VVCC = 3.3V, tpulse ≥ 1µs, auto mode 0.56 A
IHS-LIM High side peak current limit, LM6X460Q1 Duty-cycle approaches 0%. 8.3 9.5 10.7 A
ILS-LIM Low side valley current limit, LM6X460-Q1 Valley current limit on LS FET 6.4 7.4 8.3 A
IL-PEAK-MIN Minimum peak inductor current at minimum duty cycle, LM6X460-Q1 VVCC = 3.3V, tpulse ≤ 100ns, auto mode 2.0 A
IL-PEAK-MAX Minimum peak inductor current at maximum duty cycle, LM65460Q1 VVCC = 3.3V, tpulse ≥ 1µs, auto mode 0.8 A
IHS-LIM High side peak current limit, LM6X440Q1 Duty-cycle approaches 0%. 4.9 6.3 7.1 A
ILS-LIM Low side valley current limit, LM6X440-Q1 Valley current limit on LS FET 3.6 4.9 5.5 A
IL-PEAK-MIN Minimum peak inductor current at minimum duty cycle, LM6X440Q1 VVCC = 3.3V, tpulse ≤ 100ns, auto mode 1.3 A
IL-PEAK-MAX Minimum peak inductor current at maximum duty cycle, LM6X440Q1 VVCC = 3.3V, tpulse ≥ 1µs, auto mode 0.21 A
ILS-NEG-LIM Low side negative current limit for 4A, LM6X440Q1 Sinking current limit on LS FET, FPWM mode -2.0 A
ILS-NEG-LIM Low side negative current limit for 6A, LM6X460Q1 Sinking current limit on LS FET, FPWM mode -3.8 A
ILS-NEG-LIM Low side negative current limit for 8A, LM6X480Q1 Sinking current limit on LS FET, FPWM mode -5.4 A
IL-ZC-LIM Zerocross current limit VVCC = 3.3V, auto mode 70 mA
VHIC Overcurrent hiccup threshold on FB Pin LS FET On-time > 165ns, not during soft-start 0.32 V
tHIC_DLY Hiccup mode activation delay 128 256 cycles
tHIC Hiccup mode duration time 54 ms
POWER GOOD (PG PIN)
VPG-OVP-R PG overvoltage rising threshold % of FB voltage (Adj) or Bias voltage (fixed) 103 105 108 %
VPG-OVP-F PG overvoltage falling threshold % of FB voltage (Adj) or Bias voltage (fixed) 102 104 106 %
VPG-UVP-R PG undervoltage rising threshold % of FB voltage (Adj) or Bias voltage (fixed) 94 96 98 %
VPG-UVP-F PG undervoltage falling threshold % of FB voltage (Adj) or Bias voltage (fixed) 93 95 97 %
tPG-DEGLITCH-F Deglitch filter delay on PG falling edge 55 114 175 µs
tPG-DEGLITCH-R Deglitch filter delay on PG rising edge 1.4 2 4.5 ms
VIN-PG-VALID Minimum VIN for valid PG output VOL(PG) < 0.4V, RPU = 50kΩ, VPU = 5V 1.25 V
VOL-PG Output low voltage IOL = 0.5 mA, VIN = 1.25V 0.4 V
RON-PG PGOOD ON resistance IPG = 1mA 35 110 Ω
SWITCHING FREQUENCY (RT PIN)
fSW1(FPWM) Switching frequency, FPWM operation RRT = GND 1.89 2.1 2.31 MHz
fSW2(FPWM) Switching frequency, FPWM operation RRT = 15.8kΩ, 1% 900 1000 1100 kHz
fSW3(FPWM) Switching frequency, FPWM operation RRT = VCC (standalone) 360 400 440 kHz
SYNCHRONIZATION (MODE/SYNC PIN)
VIH(MODE/CLKIN) MODE/CLKIN input high level threshold 1.3 V
VIL(MODE/CLKIN) MODE/CLKIN input low level threshold 0.45 V
fCLKIN-RANGE(FPWM) Synchronization frequency range for set 2.2 MHz fSW RRT = 6.81kΩ, 1% 1.76 2.64 MHz
tCLKIN(TON) Minimum positive pulse width of external sync signal 80 ns
tCLKIN(TOFF) Minimum negative pulse width of external sync signal 80 ns
tCLKIN-SW-DLY CLKIN to SW delay time 18 30 ns
DUAL RANDOM SPREAD SPECTRUM
ΔfSS1-LF Low-frequency triangular spread spectrum modulation range - standard 8.5 %
ΔfSS2-LF Low-frequency triangular spread spectrum modulation range - extended 17 %
fm1-LF Triangular modulation frequency - standard 7.2 13 17.2 kHz
fm2-LF Triangular modulation frequency - extended 5 7 9.1 kHz
ΔfSS-HF High-frequency pseudo-random spread spectrum modulation range 2.4 %
POWER STAGE
RDS-ON-HS High-side FET ON resistance ISW = 500mA, VBOOT-SW = 3.3V 27 mΩ
RDS-ON-LS Low-side FET ON resistance 16 mΩ
tON-MIN(FPWM) Minimum on-time FPWM: IOUT = 0A, VIN = 36V, RT = GND 32 45 ns
tON-MIN(AUTO)
Minimum on-time 
 		 AUTO: IOUT = 2A, VIN = 36V, RT = GND 32 40 ns
tOFF-MIN Minimum off-time VIN = 4V 100 125 ns
tON-MAX Maximum on-time fSW = 400kHz, RRT= 40.2 kΩ 13.3 µs
THERMAL SHUTDOWN
TSD Thermal shutdown(1) Shutdown threshold 155 165 177 ºC
Recovery threshold 156 ºC
(1) Specified by design.