SPMU375 August   2025 LP8733-Q1

 

  1.   1
  2.   Trademarks
  3.   Technical Reference Manual
  4. 1Introduction
  5. 2OTP Memory Device Settings
  6. 3Power-up and Power Down Sequence
  7. 4Register Bits Loaded From OTP Memory
  8. 5Revision History

3 Power-up and Power Down Sequence

This section shows the power-up and power-down sequence for the device. The power-up and power-down delays for each rail are shown in Figure 3-1.

LP873362-Q1Power-up and Power Down Sequence Figure 3-1 LP873362-Q1Power-up and Power Down Sequence