SPMU470 November   2026 TPS65214

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521406 Power Sequence and Example Block Diagram
  6. 3NVM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Low Power Mode
  7. 4Revision History

1 Introduction

The TPS6521406 PMIC is a cost and space optimized device that has flexible mapping to support the power requirements from different processors and SoCs. The PMIC includes three Buck regulators and two low drop-out regulators (LDOs) with I2C, GPIOs, and configurable multi-function pins. The device also contains one-time programmable (OTP) non-volatile memory (NVM) that is loaded to the device registers when entering the INITIALIZE state. This document describes the default configuration programmed on the TPS6521406.

Note: The NVM configuration described in this document is a good fit for the application described below but can also be used to power other processors or SoCs with equivalent power requirements.
  • Processor: AM26x
  • CORE voltage: 1.25V
  • Input Supply (VSYS, PVIN_Bx): 5V