SPRAD13 May   2022 AM623 , AM625

 

  1.   Abstract
  2.   Trademarks
  3. Introduction
  4. Via Channel Arrays
  5. Width/Spacing Proposal for Escapes
  6. Stackup
  7. Via Sharing
  8. Floorplan Component Placement
  9. Critical Interfaces Impact Placement
  10. Routing Priority
  11. SerDes Interfaces
  12. 10DDR Interfaces
  13. 11Power Decoupling
  14. 12Route Lowest Priority Interfaces Last
  15. 13Summary

Routing Priority

As indicated above, critical interfaces will affect component placement options. The next step in PCB design is to prioritize routing to these critical interfaces. Those with higher priority must be completed before implementing those of lower priority. It is imperative to route interface with the higher priority first. PCB layout teams often end up in a time intense, iterative process with sub optimal results when routing priorities are not established.

Table 8-1 lists a recommended priority order for interfaces contained on the AM62 family of devices. Individual design requirements may drive a need for adjustment of the priorities but this serves as a good baseline and has been used for the board example illustrated in this document.

Table 8-1 Routing Priority
Interface Routing Priority
CSI 10 (Highest Priority)
DDR4/LPDDR4 9
OLDI 9
OSC 8
USB2, OSPI 8
Power distribution 7
RGMII 6
eMMC 5
Clocks 5
MII / RMII 4
SPI 4
Motor control 4
Analog 3
GPMC 2
GPIO 1
UART / CANUART 1
I2C / Temp Diode 1 (Lowest Priority)

The multi-gigabit Camera Serial Interfaces (CSI) are the most critical due to their data rate and loss concerns. CSI is at the top of the priority list because it is sensitive to PCB losses. The limited length for these routes might affect the PCB placement of the CSI connector and the AM62 device. CSI signals are found on the outer layers of the BGA footprint, allowing some of the CSI traces to escape from the BGA without vias.

The asynchronous and low speed interfaces are at the bottom. This leaves the synchronous and source-synchronous interfaces on the top ordered by data rate. The one surprise may be power distribution. It is often left to last. This then results in poor decoupling performance and/or current starvation and excessive power supply noise due to insufficient copper to carry the power and ground currents. Space for copper and decoupling needs to be allocated before routing the middle and low priority interfaces.