4 Random and Systematic Faults

There are two types of faults that can occur, random and systematic. Random fault occurrence is influenced by a number of variables, including operating temperature, power on hours, operating voltage, and neutron flux factor. Consequently, the ability to address random hardware faults is limited to detecting and possibly preventing the fault during runtime execution and putting the system into a safe state. Systematic faults result from an inadequacy in the design, development or manufacturing process and typically stem from gaps in the development process. A silicon bug is a systematic fault because the bug is detectable during the design verification phase of development.

In theory, systematic faults can be reduced to zero through tightly-controlled and adhered-to development and manufacturing processes. SIL or ASIL systematic ratings are not assigned a FIT rate like random faults, but rather define different levels of procedures and processes that must be adhered to. To meet systematic capability requirements for both IEC 61508 and ISO 26262, TI developed an internal safety IC development standard which was certified by TÜV SÜD, an independent third-party assessor. TI certifications for safety hardware and software development can be found on the TI functional safety home page.

Unlike systematic faults, random faults can never be reduced to zero and must be managed to an acceptable level through the use of different techniques. For ICs, the number of random hardware faults can be reduced to an acceptable SIL or ASIL level by using system-level design techniques, manufacturing in a low FIT rate silicon process, and implementing both hardware and software safety diagnostics. Section 5 describes what is meant by safety diagnostics and provides use examples in the AM243x and AM64x devices.