Product details

TI.com inventory 451 Frequency (MHz) 800 RAM (KB) 2000 ADC 12-bit SAR GPIO 148, 198 UART 7, 9 Operating temperature range (C) -40 to 105, -40 to 125 Ethernet Yes
TI.com inventory 451 Frequency (MHz) 800 RAM (KB) 2000 ADC 12-bit SAR GPIO 148, 198 UART 7, 9 Operating temperature range (C) -40 to 105, -40 to 125 Ethernet Yes
FCBGA (ALV) 441 296 mm² 17.2 x 17.2 FCBGA (ALV) 441 FCCSP (ALX) 293
  • Up to 2× Dual-core Arm Cortex-R5F MCU subsystems operating at up to 800 MHz, highly-integrated for real-time processing
    • Dual-core Arm Cortex-R5F clusters support dual-core and single-core operation
    • 32KB ICache and 32KB DCache per R5F core with SECDED ECC on all memories
    • Single-core: 128KB TCM per cluster (128KB TCM per R5F core)
    • Dual-core: 128KB TCM per cluster (64KB TCM per R5F core)
  • 1× Single-core Arm Cortex-M4F MCU at up to 400 MHz
    • 256KB SRAM with SECDED ECC
  • Up to 2MB of On-chip RAM (OCSRAM) with SECDED ECC:
    • Can be divided into smaller banks in increments of 256KB for as many as 8 separate memory banks
    • Each memory bank can be allocated to a single core to facilitate software task partitioning
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4, DDR4 memory types
    • 16-Bit data bus with inline ECC
    • Supports speeds up to 1600 MT/s
  • Device Management Security Controller (DMSC-L)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, and clock/reset/power management
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals
    • On-Chip Debug functionality through JTAG and Trace interfaces)
  • Data Movement Subsystem (DMSS)
    • Block Copy DMA (BCDMA)
    • Packet DMA (PKTDMA)
    • Secure Proxy (SEC_PROXY)
    • Ring Accelerator (RINGACC)
  • Time Sync Subsystem
    • Central Platform Time Sync (CPTS) module
    • Timer Manager (TIMERMANAGER) with 1024 timers
    • Time Sync and Compare event interrupt routers
  • 2× Gigabit Industrial Communication Subsystems (PRU_ICSSG)
    • Optional support for Profinet IRT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and other Networking Protocols
    • Backwards compatibility with 10/100Mb PRU_ICSS
    • Each PRU_ICSSG contains:
      • 3× PRU RISC Cores per Slice (2× Slice per PRU_ICSSG)
        • PRU General Use core (PRU)
        • PRU Real-Time Unit core (PRU-RTU)
        • PRU Transmit core (PRU-TX)
      • Each PRU core supports the following features:
        • Instruction RAM with ECC
        • Broadside RAM
        • Multiplier with optional accumulator (MAC)
        • CRC16/32 hardware accelerator
        • Byte swap for Big/Little Endian conversion
        • SUM32 hardware accelerator for UDP checksum
        • Task Manager for preemption support
      • Up to 2× Ethernet ports
        • RGMII (10/100/1000)
        • MII (10/100)
      • Three Data RAMs with ECC
      • 8 banks of 30 × 32-bit register scratchpad memory
      • Interrupt controller and task manager
      • 2× 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions
      • 18× Sigma-Delta Filter Module (SDFM) interfaces
        • Short circuit logic
        • Over-current logic
      • 6× Multi-protocol position encoder interfaces
      • 1× Enhanced Capture Module (ECAP)
      • 16550-compatible UART
        • Dedicated 192-MHz clock to support 12-Mbps PROFIBUS
  • Secure Boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Support for cryptographic acceleration
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
    • DMA support
    • Supports cryptographic cores
      • AES – 128/192/256-bit key sizes
      • 3DES – 56/112/168-bit key sizes
      • MD5, SHA1
      • SHA2 – 224/256/384/512-bit key sizes
      • DRBG with true random number generator
      • PKA (Public Key Accelerator) to Assist in RSA/ECC processing
  • Debugging security
    • Secure software-controlled debug access
    • Security aware debugging
  • Secure storage support
  • On-the-Fly encryption (OTFE) support for OSPI in XIP mode
  • Networking security support for data (Payload) encryption/authentication via packet-based hardware cryptographic engine
  • DMSC-L co-processor for security and key management, with dedicated device level interconnect
  • 6× Inter-Integrated Circuit (I2C) ports
  • 9× configurable Universal Asynchronous Receive/Transmit (UART) modules
  • 1× 12-bit Analog-to-Digital Converters (ADC)
    • Configurable sample rate up to 4 MSPS
    • 8× multiplexed analog inputs
  • 7× Multichannel Serial Peripheral Interfaces (SPI) controllers
  • 3× General-Purpose I/O (GPIO) modules
  • 9× Enhanced Pulse-Width Modulator (EPWM) modules
  • 3× Enhanced Capture (ECAP) modules
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules
  • 2× Modular Controller Area Network (MCAN) modules with full CAN-FD support
  • 2× Fast Serial Interface Transmitter (FSITX) cores
  • 6× Fast Serial Interface Receiver (FSIRX) cores
  • 1× Integrated Ethernet switch supporting up to 2 external ports (CPSW3G)
    • Up to 2 Ethernet ports
      • RGMII (10/100/1000)
      • RMII (10/100)
    • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Clause 45 MDIO PHY management
    • Energy efficient Ethernet (802.3az)
  • 1× PCI-Express Gen2 controller (PCIE)
    • Supports Gen2 Single Lane operation
  • 1× USB 3.1 Dual-Role Device (DRD) Subsystem (USBSS)
    • Port configurable as USB host, USB device, or USB Dual-Role device
    • USB device: High-speed (480 Mbps) and Full-speed (12 Mbps)
    • USB host: SuperSpeed Gen 1 (5 Gbps), High-speed (480 Mbps),Full-speed (12 Mbps), and Low-speed (1.5 Mbps)
    • Integrated USB VBUS detection
  • 1× Serializer/Deserializer (SERDES)
    • One SerDes PHY lane to support either PCI-Express Gen2 or USB Super-Speed Gen1
  • 2× MultiMedia Card/Secure Digital (MMCSD) interfaces
    • One 8-bit for eMMC (MMCSD0)
    • One 4-bit for SD/SDIO (MMCSD1)
    • Integrated analog switch for voltage switching between 3.3V to 1.8V for high-speed cards
  • 1× General-Purpose Memory Controller (GPMC)
    • 16-bit parallel bus with 133 MHz clock or
    • 32-bit parallel bus with 100 MHz clock
    • Error Location Module (ELM) support
  • 1× Flash Subsystem (FSS) that can be configured as one Octal SPI (OSPI) or one Quad SPI (QSPI) flash interface
  • Simplified power sequencing requirements
  • Dual-voltage I/O Support
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated voltage supervisor for safety monitoring of over-under voltage conditions
  • Integrated power supply glitch detector for detecting fast supply transients
  • Functional Safety-compliant Targeted
    • Developed for functional safety applications
    • Documentation available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3
    • Hardware integrity up to SIL 2 targeted
    • Safety-related certification
      • IEC 61508 certification planned
    • ECC or parity on calculation-critical memories
    • ECC and parity on select internal bus interconnects
    • Built-In Self-Test (BIST) for CPU and on-chip RAM
    • Error Signaling Module (ESM) with external error pin
    • Run-time safety diagnostics, including:
      • Voltage, Temperature, and Clock Monitoring
      • Windowed Watchdog Timers
      • CRC Engine for memory integrity checks
    • MCU domain with dedicated memory, interfaces, and M4F core capable of being isolated from the larger SoC with Freedom From Interference (FFI) features:
      • Separate interconnect
      • Firewalls and timeout gaskets
      • Controlled reset isolation
      • Dedicated MCU PLL and MMR control
      • Separate I/O Voltage Supply Rail
  • Supports primary boot from UART, I2C, OSPI/QSPI Flash, SPI Flash, parallel NOR Flash, parallel NAND Flash, SD, eMMC, USB 2.0, PCIe, and Ethernet interfaces
  • 16-nm FinFET technology
  • ALV: 17.2 mm × 17.2 mm, 0.8 mm pitch (441-pin) FCBGA [Lidded] Flip-Chip Ball Grid Array ALV package
  • ALX: 11.0 mm × 11.0 mm, 0.5 mm pitch (293-pin) FC/CSP [SiP] Flip-Chip/Chip Scale Package ALX package  
  • Up to 2× Dual-core Arm Cortex-R5F MCU subsystems operating at up to 800 MHz, highly-integrated for real-time processing
    • Dual-core Arm Cortex-R5F clusters support dual-core and single-core operation
    • 32KB ICache and 32KB DCache per R5F core with SECDED ECC on all memories
    • Single-core: 128KB TCM per cluster (128KB TCM per R5F core)
    • Dual-core: 128KB TCM per cluster (64KB TCM per R5F core)
  • 1× Single-core Arm Cortex-M4F MCU at up to 400 MHz
    • 256KB SRAM with SECDED ECC
  • Up to 2MB of On-chip RAM (OCSRAM) with SECDED ECC:
    • Can be divided into smaller banks in increments of 256KB for as many as 8 separate memory banks
    • Each memory bank can be allocated to a single core to facilitate software task partitioning
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4, DDR4 memory types
    • 16-Bit data bus with inline ECC
    • Supports speeds up to 1600 MT/s
  • Device Management Security Controller (DMSC-L)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, and clock/reset/power management
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals
    • On-Chip Debug functionality through JTAG and Trace interfaces)
  • Data Movement Subsystem (DMSS)
    • Block Copy DMA (BCDMA)
    • Packet DMA (PKTDMA)
    • Secure Proxy (SEC_PROXY)
    • Ring Accelerator (RINGACC)
  • Time Sync Subsystem
    • Central Platform Time Sync (CPTS) module
    • Timer Manager (TIMERMANAGER) with 1024 timers
    • Time Sync and Compare event interrupt routers
  • 2× Gigabit Industrial Communication Subsystems (PRU_ICSSG)
    • Optional support for Profinet IRT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and other Networking Protocols
    • Backwards compatibility with 10/100Mb PRU_ICSS
    • Each PRU_ICSSG contains:
      • 3× PRU RISC Cores per Slice (2× Slice per PRU_ICSSG)
        • PRU General Use core (PRU)
        • PRU Real-Time Unit core (PRU-RTU)
        • PRU Transmit core (PRU-TX)
      • Each PRU core supports the following features:
        • Instruction RAM with ECC
        • Broadside RAM
        • Multiplier with optional accumulator (MAC)
        • CRC16/32 hardware accelerator
        • Byte swap for Big/Little Endian conversion
        • SUM32 hardware accelerator for UDP checksum
        • Task Manager for preemption support
      • Up to 2× Ethernet ports
        • RGMII (10/100/1000)
        • MII (10/100)
      • Three Data RAMs with ECC
      • 8 banks of 30 × 32-bit register scratchpad memory
      • Interrupt controller and task manager
      • 2× 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions
      • 18× Sigma-Delta Filter Module (SDFM) interfaces
        • Short circuit logic
        • Over-current logic
      • 6× Multi-protocol position encoder interfaces
      • 1× Enhanced Capture Module (ECAP)
      • 16550-compatible UART
        • Dedicated 192-MHz clock to support 12-Mbps PROFIBUS
  • Secure Boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Support for cryptographic acceleration
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
    • DMA support
    • Supports cryptographic cores
      • AES – 128/192/256-bit key sizes
      • 3DES – 56/112/168-bit key sizes
      • MD5, SHA1
      • SHA2 – 224/256/384/512-bit key sizes
      • DRBG with true random number generator
      • PKA (Public Key Accelerator) to Assist in RSA/ECC processing
  • Debugging security
    • Secure software-controlled debug access
    • Security aware debugging
  • Secure storage support
  • On-the-Fly encryption (OTFE) support for OSPI in XIP mode
  • Networking security support for data (Payload) encryption/authentication via packet-based hardware cryptographic engine
  • DMSC-L co-processor for security and key management, with dedicated device level interconnect
  • 6× Inter-Integrated Circuit (I2C) ports
  • 9× configurable Universal Asynchronous Receive/Transmit (UART) modules
  • 1× 12-bit Analog-to-Digital Converters (ADC)
    • Configurable sample rate up to 4 MSPS
    • 8× multiplexed analog inputs
  • 7× Multichannel Serial Peripheral Interfaces (SPI) controllers
  • 3× General-Purpose I/O (GPIO) modules
  • 9× Enhanced Pulse-Width Modulator (EPWM) modules
  • 3× Enhanced Capture (ECAP) modules
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules
  • 2× Modular Controller Area Network (MCAN) modules with full CAN-FD support
  • 2× Fast Serial Interface Transmitter (FSITX) cores
  • 6× Fast Serial Interface Receiver (FSIRX) cores
  • 1× Integrated Ethernet switch supporting up to 2 external ports (CPSW3G)
    • Up to 2 Ethernet ports
      • RGMII (10/100/1000)
      • RMII (10/100)
    • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Clause 45 MDIO PHY management
    • Energy efficient Ethernet (802.3az)
  • 1× PCI-Express Gen2 controller (PCIE)
    • Supports Gen2 Single Lane operation
  • 1× USB 3.1 Dual-Role Device (DRD) Subsystem (USBSS)
    • Port configurable as USB host, USB device, or USB Dual-Role device
    • USB device: High-speed (480 Mbps) and Full-speed (12 Mbps)
    • USB host: SuperSpeed Gen 1 (5 Gbps), High-speed (480 Mbps),Full-speed (12 Mbps), and Low-speed (1.5 Mbps)
    • Integrated USB VBUS detection
  • 1× Serializer/Deserializer (SERDES)
    • One SerDes PHY lane to support either PCI-Express Gen2 or USB Super-Speed Gen1
  • 2× MultiMedia Card/Secure Digital (MMCSD) interfaces
    • One 8-bit for eMMC (MMCSD0)
    • One 4-bit for SD/SDIO (MMCSD1)
    • Integrated analog switch for voltage switching between 3.3V to 1.8V for high-speed cards
  • 1× General-Purpose Memory Controller (GPMC)
    • 16-bit parallel bus with 133 MHz clock or
    • 32-bit parallel bus with 100 MHz clock
    • Error Location Module (ELM) support
  • 1× Flash Subsystem (FSS) that can be configured as one Octal SPI (OSPI) or one Quad SPI (QSPI) flash interface
  • Simplified power sequencing requirements
  • Dual-voltage I/O Support
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated voltage supervisor for safety monitoring of over-under voltage conditions
  • Integrated power supply glitch detector for detecting fast supply transients
  • Functional Safety-compliant Targeted
    • Developed for functional safety applications
    • Documentation available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3
    • Hardware integrity up to SIL 2 targeted
    • Safety-related certification
      • IEC 61508 certification planned
    • ECC or parity on calculation-critical memories
    • ECC and parity on select internal bus interconnects
    • Built-In Self-Test (BIST) for CPU and on-chip RAM
    • Error Signaling Module (ESM) with external error pin
    • Run-time safety diagnostics, including:
      • Voltage, Temperature, and Clock Monitoring
      • Windowed Watchdog Timers
      • CRC Engine for memory integrity checks
    • MCU domain with dedicated memory, interfaces, and M4F core capable of being isolated from the larger SoC with Freedom From Interference (FFI) features:
      • Separate interconnect
      • Firewalls and timeout gaskets
      • Controlled reset isolation
      • Dedicated MCU PLL and MMR control
      • Separate I/O Voltage Supply Rail
  • Supports primary boot from UART, I2C, OSPI/QSPI Flash, SPI Flash, parallel NOR Flash, parallel NAND Flash, SD, eMMC, USB 2.0, PCIe, and Ethernet interfaces
  • 16-nm FinFET technology
  • ALV: 17.2 mm × 17.2 mm, 0.8 mm pitch (441-pin) FCBGA [Lidded] Flip-Chip Ball Grid Array ALV package
  • ALX: 11.0 mm × 11.0 mm, 0.5 mm pitch (293-pin) FC/CSP [SiP] Flip-Chip/Chip Scale Package ALX package  

AM243x is an extension of Sitara’s industrial-grade portfolio into high-performance microcontrollers. The AM243x device is built for industrial applications, such as motor drives and remote I/O modules, which require a combination of real-time communications and processing. The AM243x family provides scalable performance with up to four Cortex-R5F MCUs, one Cortex-M4F, and two instances of Sitara’s gigabit TSN-enabled PRU_ICSSG.

The AM243x SoC architecture was designed to provide best-in-class real-time performance through the high-performance Arm Cortex-R5F cores, Tightly-Coupled Memory banks, configurable SRAM partitioning, and dedicated low-latency paths to and from peripherals for rapid data movement in and out of the SoC. This deterministic architecture allows for AM243x to handle the tight control loops found in servo drives while the peripherals like FSI, GPMC, ECAPs, PWMs, and encoder interfaces help enable a number of different architectures found in these systems.

The SoC provides flexible industrial communications capability including full protocol stacks for EtherCAT target, PROFINET device, EtherNet/IP adapter, and IO-Link Controller. The PRU_ICSSG further provides capability for gigabit and TSN based protocols. In addition, the PRU_ICSSG enables additional interfaces including a UART interface, sigma delta decimation filters, and absolute encoder interfaces.

Functional safety features can be enabled through the integrated Cortex-M4F along with dedicated peripherals which can all be isolated from the rest of the SoC. AM243x also supports secure boot.

AM243x is an extension of Sitara’s industrial-grade portfolio into high-performance microcontrollers. The AM243x device is built for industrial applications, such as motor drives and remote I/O modules, which require a combination of real-time communications and processing. The AM243x family provides scalable performance with up to four Cortex-R5F MCUs, one Cortex-M4F, and two instances of Sitara’s gigabit TSN-enabled PRU_ICSSG.

The AM243x SoC architecture was designed to provide best-in-class real-time performance through the high-performance Arm Cortex-R5F cores, Tightly-Coupled Memory banks, configurable SRAM partitioning, and dedicated low-latency paths to and from peripherals for rapid data movement in and out of the SoC. This deterministic architecture allows for AM243x to handle the tight control loops found in servo drives while the peripherals like FSI, GPMC, ECAPs, PWMs, and encoder interfaces help enable a number of different architectures found in these systems.

The SoC provides flexible industrial communications capability including full protocol stacks for EtherCAT target, PROFINET device, EtherNet/IP adapter, and IO-Link Controller. The PRU_ICSSG further provides capability for gigabit and TSN based protocols. In addition, the PRU_ICSSG enables additional interfaces including a UART interface, sigma delta decimation filters, and absolute encoder interfaces.

Functional safety features can be enabled through the integrated Cortex-M4F along with dedicated peripherals which can all be isolated from the rest of the SoC. AM243x also supports secure boot.

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Technical documentation

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Type Title Date
* Data sheet AM243x Sitara™ Microcontrollers datasheet (Rev. F) PDF | HTML 09 Jan 2023
* Errata AM64x/AM243x Processor Silicon Revision 1.0, 2.0 (Rev. F) PDF | HTML 13 Oct 2022
* User guide AM64x/AM243x Technical Reference Manual (Rev. E) 01 Nov 2022
Application note FSI Bandwidth-Optimization for Multi-axis Servo Control PDF | HTML 14 Dec 2022
Application note Debugging Sitara AM2x Microcontrollers PDF | HTML 24 Oct 2022
Application note Optimized Trigonometric Functions on TI Arm Cores (Rev. A) PDF | HTML 08 Aug 2022
Application note AM64x/AM243x Extended Power-On Hours PDF | HTML 05 Aug 2022
Application note High-Speed Interface Layout Guidelines (Rev. I) PDF | HTML 14 Apr 2022
Technical article What is “real-time control” and why do you need it? 06 Apr 2022
Application note AM243x/AM64x Single Chip Motor Control Benchmark PDF | HTML 30 Mar 2022
Technical article Factory automation design made simple with multiprotocol industrial Ethernet systems 15 Mar 2022
Application note Using LP8733xx and TPS65218xx PMICs to Power AM64x and AM243x Sitara Processors PDF | HTML 16 Feb 2022
Application note Sitara™AM64x /AM243x BenchmarksCortex-R5 Memory Access Latency (Rev. A) PDF | HTML 15 Feb 2022
White paper Industry 4.0 서보 드라이브에 Sitara™ 프로세서 및 마이크로컨트롤러 활용 (Rev. C) PDF | HTML 12 Jan 2022
White paper 運用適合工業 4.0 Sitara™ 伺服驅動器的處理器與微控制器 (Rev. C) PDF | HTML 12 Jan 2022
White paper Utilizing Sitara Processors and Microcontrollers for Industry 4.0 Servo Drives (Rev. C) 06 Oct 2021
Application note Industrial Communication Protocols Supported on Sitara™ Processors (Rev. D) PDF | HTML 30 Sep 2021
Application note AM64x/AM243x Schematic Review Checklist (Rev. B) PDF | HTML 20 Aug 2021
Technical article 5 ways high-performance MCUs are reshaping the industry 12 Jul 2021
White paper Revolutionizing Real-Time Control, Networking and Analytics w/ Sitara™ AM2x MCUs PDF | HTML 07 Jul 2021
Application note AM64x/AM243x DDR Board Design and Layout Guidelines (Rev. A) PDF | HTML 01 Jul 2021
Application note AM64x/AM243x Power Estimation Tool (Rev. A) PDF | HTML 01 Jul 2021
More literature LaunchPad™ kit with Sitara™ AM243x MCU Pinout Map 18 Jun 2021
White paper Sitara™ AM2x MCU를 통한 실시간 제어, 네트워킹 및 분석 성능 혁신 13 Jun 2021
White paper 以 Sitara™ AM2x MCU 顛覆即時控制、網路與分析效能 13 Jun 2021
User guide AM64x/AM243x BGA Escape Routing (Rev. A) PDF | HTML 06 Apr 2021
Functional safety information The state of functional safety in Industry 4.0 27 Nov 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LP-AM243 — AM243x LaunchPad™ development kit for Arm® Cortex®-R5F-based MCUs

LP-AM243 is a development board for Sitara™ high performance microcontrollers from the AM243x series.-This board is ideal for initial evaluation and prototyping as it provides a standardized and easy-to-use platform to develop your next application. The LP-AM243 is equipped with a (...)

User guide: PDF | HTML
Not available on TI.com
Evaluation board

TMDS243DC01EVM — AM243x and AM64x evaluation module breakout board for high-speed expansion

TMDS243DC01EVM is the high-speed expansion (HSE) evaluation module (EVM) for AM243x products. This EVM is an add-on board for the AM243x general-purpose EVM (TMDS243GPEVM).

TMDS243DC01EVM includes a general-purpose signal breakout that provides test access to all the I/O signals included on the HSE (...)

User guide: PDF | HTML
Not available on TI.com
Evaluation board

TMDS243EVM — AM243x evaluation module for Arm® Cortex®-R5F-based MCUs

Note that TMDS243EVM is the newest version of TMS243GPEVM. TMDS243EVM includes high-security field-securable (HS-FS) silicon to customize keys and encryption for security applications.

The TMDS243 evaluation module (EVM) is a standalone test and development platform for evaluating AM243x (...)

User guide: PDF | HTML
Not available on TI.com
Evaluation board

TMDS243GPEVM — AM243x general-purpose evaluation module for Arm® Cortex®-R5F-based MCUs

The AM243x EVM is a standalone test, development, and evaluation module (EVM) that lets developers evaluate AM243x's functionality and develop prototypes for a variety of applications.

The EVM is equipped with a Sitara™ AM2434 processor along with additional components to allow the user to (...)

User guide: PDF | HTML
Not available on TI.com
Evaluation board

PHYTC-3P-KIT-AM64 — PHYTEC® phyBOARD®-AM64x development kit with AM6442 Arm®-based Sitara™ processor

PHYTEC is an industry-leading provider and integrator of system on modules (SoMs), embedded middleware and design services that enable customers to bring complex products quickly and easily to market. They guide customers from design to production utilizing deep domain expertise, high-quality (...)

From: PHYTEC
Software development kit (SDK)

MCU-PLUS-SDK-AM243X — AM243x software development kit (SDK) for Sitara™ microcontrollers

The MCU+ software development kit (SDK) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to examples, benchmarks and demos.  This software accelerates application development schedules by eliminating the need to create basic system (...)
IDE, configuration, compiler or debugger

IAR-KICKSTART — IAR Embedded Workbench

IAR Embedded Workbench delivers a complete development toolchain for building and debugging embedded applications for your selected target microcontroller. The included IAR C/C++ Compiler generates highly optimized code for your application, and the C-SPY Debugger is a fully integrated debugger for (...)
From: IAR Systems
IDE, configuration, compiler or debugger

SYSCONFIG — System configuration tool

To help simplify configuration challenges and accelerate software development, we created SysConfig, an intuitive and comprehensive collection of graphical utilities for configuring pins, peripherals, radios, subsystems, and other components.  SysConfig helps you manage, expose and resolve (...)
Support software

AM243x SW Build Sheet

SPRCAJ9.ZIP (21 KB)
Simulation model

AM243x BSDL Model

SPRM781.ZIP (17 KB) - BSDL Model
Simulation model

AM243x IBIS model (Rev. B)

SPRM783B.ZIP (263 KB) - IBIS Model
Simulation model

AM243x Thermal Model

SPRM782.ZIP (1 KB) - Thermal Model
Simulation model

AM64x Power Estimation Tool

SPRM779.ZIP (96 KB) - Power Model
Simulation model

AM64x/AM243x BSDL Model

SPRM732.ZIP (21 KB) - BSDL Model
Simulation model

AM64x/AM243x IBIS Model (Rev. C)

SPRM730C.ZIP (1889 KB) - IBIS Model
Simulation model

AM64x/AM243x Thermal Model

SPRM773.ZIP (2 KB) - Thermal Model
Design tool

PROCESSORS-3P-SEARCH — Arm®-based MPU, Arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
Reference designs

TIDA-010234 — Eight-port IO-Link master reference design

This reference design implements an IO-Link master with fast and deterministic timing with eight ports. Each port can be operated with independent bit rate and cycle timing. This design can be used to build a remote IO gateway to connect to OPC UA, Profinet, EtherCAT or Ethernet IP. A PRU-based (...)
Design guide: PDF
Package Pins Download
FCBGA (ALV) 441 View options
FCCSP (ALX) 293 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
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