SPRSPC5 May   2026 TMS320F28P551SG

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      4. 5.4.4 GPIO Input X-BAR
      5. 5.4.5 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  IC Latch-Up Test: JESD78F.02
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Power Consumption Summary
      1. 6.6.1 System Current Consumption - VREG Enable - Internal Supply
      2. 6.6.2 System Current Consumption - VREG Disable - External Supply
      3. 6.6.3 Operating Mode Test Description
      4. 6.6.4 Current Consumption Graphs
      5. 6.6.5 Reducing Current Consumption
        1. 6.6.5.1 Typical Current Reduction per Disabled Peripheral
    7. 6.7  Electrical Characteristics
    8. 6.8  Special Considerations for 5V Fail-Safe Pins
    9. 6.9  Thermal Resistance Characteristics for PZ Package
    10. 6.10 Thermal Resistance Characteristics for PN and PNA Packages
    11. 6.11 Thermal Resistance Characteristics for PM Package
    12. 6.12 Thermal Resistance Characteristics for RSH Package
    13. 6.13 Thermal Resistance Characteristics for YAF Package
    14. 6.14 Thermal Resistance Characteristics for ZNG Package
    15. 6.15 Thermal Design Considerations
    16. 6.16 System
      1. 6.16.1  Power Management Module (PMM)
        1. 6.16.1.1 Introduction
        2. 6.16.1.2 Overview
          1. 6.16.1.2.1 Power Rail Monitors
            1. 6.16.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.16.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.16.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.16.1.2.2 External Supervisor Usage
          3. 6.16.1.2.3 Delay Blocks
          4. 6.16.1.2.4 Internal VDD LDO Voltage Regulator (VREG)
          5. 6.16.1.2.5 VREGENZ
        3. 6.16.1.3 External Components
          1. 6.16.1.3.1 Decoupling Capacitors
            1. 6.16.1.3.1.1 VDDIO Decoupling
            2. 6.16.1.3.1.2 VDD Decoupling
        4. 6.16.1.4 Power Sequencing
          1. 6.16.1.4.1 Supply Pins Ganging
          2. 6.16.1.4.2 Signal Pins Power Sequence
          3. 6.16.1.4.3 Supply Pins Power Sequence
            1. 6.16.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.16.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.16.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.16.1.4.3.4 Supply Slew Rate
        5. 6.16.1.5 Recommended Operating Conditions Applicability to the PMM
        6. 6.16.1.6 Power Management Module Electrical Data and Timing
          1. 6.16.1.6.1 Power Management Module Operating Conditions
          2. 6.16.1.6.2 Power Management Module Characteristics
      2. 6.16.2  Reset Timing
        1. 6.16.2.1 Reset Sources
        2. 6.16.2.2 Reset Electrical Data and Timing
          1. 6.16.2.2.1 Reset - XRSn - Timing Requirements
          2. 6.16.2.2.2 Reset - XRSn - Switching Characteristics
          3. 6.16.2.2.3 Reset Timing Diagrams
      3. 6.16.3  Clock Specifications
        1. 6.16.3.1 Clock Sources
        2. 6.16.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.16.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.16.3.2.1.1 Input Clock Frequency
            2. 6.16.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.16.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source - Not a Crystal
            4. 6.16.3.2.1.4 X1 Timing Requirements
            5. 6.16.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.16.3.2.1.6 APLL Characteristics
            7. 6.16.3.2.1.7 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled
            8. 6.16.3.2.1.8 Internal Clock Frequencies
        3. 6.16.3.3 Input Clocks and PLLs
        4. 6.16.3.4 XTAL Oscillator
          1. 6.16.3.4.1 Introduction
          2. 6.16.3.4.2 Overview
            1. 6.16.3.4.2.1 Electrical Oscillator
              1. 6.16.3.4.2.1.1 Modes of Operation
                1. 6.16.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.16.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.16.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.16.3.4.2.2 Quartz Crystal
            3. 6.16.3.4.2.3 GPIO Modes of Operation
          3. 6.16.3.4.3 Functional Operation
            1. 6.16.3.4.3.1 ESR – Effective Series Resistance
            2. 6.16.3.4.3.2 Rneg – Negative Resistance
            3. 6.16.3.4.3.3 Start-up Time
              1. 6.16.3.4.3.3.1 X1/X2 Precondition
            4. 6.16.3.4.3.4 DL – Drive Level
          4. 6.16.3.4.4 How to Choose a Crystal
          5. 6.16.3.4.5 Testing
          6. 6.16.3.4.6 Common Problems and Debug Tips
          7. 6.16.3.4.7 Crystal Oscillator Specifications
            1. 6.16.3.4.7.1 Crystal Equivalent Series Resistance (ESR) Requirements
            2. 6.16.3.4.7.2 Crystal Oscillator Parameters
            3. 6.16.3.4.7.3 Crystal Oscillator Electrical Characteristics
        5. 6.16.3.5 Internal Oscillators
          1. 6.16.3.5.1 INTOSC Characteristics
      4. 6.16.4  Flash Parameters
        1. 6.16.4.1 Flash Parameters 
      5. 6.16.5  RAM Specifications
      6. 6.16.6  ROM Specifications
      7. 6.16.7  Emulation/JTAG
        1. 6.16.7.1 JTAG Electrical Data and Timing
          1. 6.16.7.1.1 JTAG Timing Requirements
          2. 6.16.7.1.2 JTAG Switching Characteristics
          3. 6.16.7.1.3 JTAG Timing Diagram
        2. 6.16.7.2 cJTAG Electrical Data and Timing
          1. 6.16.7.2.1 cJTAG Timing Requirements
          2. 6.16.7.2.2 cJTAG Switching Characteristics
          3. 6.16.7.2.3 cJTAG Timing Diagram
      8. 6.16.8  GPIO Electrical Data and Timing
        1. 6.16.8.1 GPIO – Output Timing
          1. 6.16.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.16.8.1.2 General-Purpose Output Timing Diagram
        2. 6.16.8.2 GPIO – Input Timing
          1. 6.16.8.2.1 General-Purpose Input Timing Requirements
          2. 6.16.8.2.2 Sampling Mode
        3. 6.16.8.3 Sampling Window Width for Input Signals
      9. 6.16.9  Interrupts
        1. 6.16.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.16.9.1.1 External Interrupt Timing Requirements
          2. 6.16.9.1.2 External Interrupt Switching Characteristics
          3. 6.16.9.1.3 External Interrupt Timing
      10. 6.16.10 Low-Power Modes
        1. 6.16.10.1 Clock-Gating Low-Power Modes
        2. 6.16.10.2 Low-Power Mode Wake-up Timing
          1. 6.16.10.2.1 IDLE Mode Timing Requirements
          2. 6.16.10.2.2 IDLE Mode Switching Characteristics
          3. 6.16.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.16.10.2.4 STANDBY Mode Timing Requirements
          5. 6.16.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.16.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.16.10.2.7 HALT Mode Timing Requirements
          8. 6.16.10.2.8 HALT Mode Switching Characteristics
          9. 6.16.10.2.9 HALT Entry and Exit Timing Diagram
    17. 6.17 Analog Peripherals
      1. 6.17.1 Block Diagram
      2. 6.17.2 Analog Pins and Internal Connections
      3. 6.17.3 Analog Signal Descriptions
      4. 6.17.4 Analog-to-Digital Converter (ADC)
        1. 6.17.4.1 ADC Configurability
          1. 6.17.4.1.1 Signal Mode
        2. 6.17.4.2 ADC Electrical Data and Timing
          1. 6.17.4.2.1 ADC Operating Conditions
          2. 6.17.4.2.2 ADC Characteristics
          3. 6.17.4.2.3 ADC INL and DNL
          4. 6.17.4.2.4 ADC Performance Per Pin
          5. 6.17.4.2.5 ADC Input Model
          6. 6.17.4.2.6 ADC Timing Diagrams
      5. 6.17.5 Temperature Sensor
        1. 6.17.5.1 Temperature Sensor Electrical Data and Timing
          1. 6.17.5.1.1 Temperature Sensor Characteristics
      6. 6.17.6 Comparator Subsystem (CMPSS)
        1. 6.17.6.1 CMPx_DACL
        2. 6.17.6.2 CMPSS Connectivity Diagram
        3. 6.17.6.3 Block Diagram
        4. 6.17.6.4 CMPSS Electrical Data and Timing
          1. 6.17.6.4.1 CMPSS Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.17.6.4.2 CMPSS DAC Static Electrical Characteristics
          4. 6.17.6.4.3 CMPSS Illustrative Graphs
          5. 6.17.6.4.4 Buffered Output from CMPx_DACL Operating Conditions
          6. 6.17.6.4.5 Buffered Output from CMPx_DACL Electrical Characteristics
      7. 6.17.7 Buffered Digital-to-Analog Converter (DAC)
        1. 6.17.7.1 Buffered DAC Electrical Data and Timing
          1. 6.17.7.1.1 Buffered DAC Operating Conditions
          2. 6.17.7.1.2 Buffered DAC Electrical Characteristics
      8. 6.17.8 Programmable Gain Amplifier (PGA)
        1. 6.17.8.1 PGA Electrical Data and Timing
          1. 6.17.8.1.1 PGA Operating Conditions
          2. 6.17.8.1.2 PGA Characteristics
    18. 6.18 Control Peripherals
      1. 6.18.1 Enhanced Pulse Width Modulator (ePWM)
        1. 6.18.1.1 Control Peripherals Synchronization
        2. 6.18.1.2 ePWM Electrical Data and Timing
          1. 6.18.1.2.1 ePWM Timing Requirements
          2. 6.18.1.2.2 ePWM Switching Characteristics
          3. 6.18.1.2.3 Trip-Zone Input Timing
            1. 6.18.1.2.3.1 Trip-Zone Input Timing Requirements
            2. 6.18.1.2.3.2 PWM Hi-Z Characteristics Timing Diagram
      2. 6.18.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.18.2.1 HRPWM Electrical Data and Timing
          1. 6.18.2.1.1 High-Resolution PWM Characteristics
      3. 6.18.3 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.18.3.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.18.3.2 ADCSOCAO or ADCSOCBO Timing Diagram
      4. 6.18.4 Enhanced Capture (eCAP)
        1. 6.18.4.1 eCAP Block Diagram
        2. 6.18.4.2 eCAP Synchronization
        3. 6.18.4.3 eCAP Electrical Data and Timing
          1. 6.18.4.3.1 eCAP Timing Requirements
          2. 6.18.4.3.2 eCAP Switching Characteristics
      5. 6.18.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.18.5.1 eQEP Electrical Data and Timing
          1. 6.18.5.1.1 eQEP Timing Requirements
          2. 6.18.5.1.2 eQEP Switching Characteristics
      6. 6.18.6 Sigma-Delta Filter Module (SDFM)
        1. 6.18.6.1 SDFM Electrical Data and Timing
          1. 6.18.6.1.1 SDFM Electrical Data and Timing (Synchronized GPIO)
          2. 6.18.6.1.2 SDFM Electrical Data and Timing (Using ASYNC)
          3. 6.18.6.1.3 SDFM Timing Requirements When Using Asynchronous GPIO - ASYNC - Option
          4. 6.18.6.1.4 SDFM Timing Requirements When Using Synchronous GPIO SYNC Option
          5. 6.18.6.1.5 SDFM Timing Diagram
    19. 6.19 Communications Peripherals
      1. 6.19.1 Modular Controller Area Network (MCAN)
      2. 6.19.2 Inter-Integrated Circuit (I2C)
        1. 6.19.2.1 I2C Electrical Data and Timing
          1. 6.19.2.1.1 I2C Timing Requirements
          2. 6.19.2.1.2 I2C Switching Characteristics
          3. 6.19.2.1.3 I2C Timing Diagram
      3. 6.19.3 Power Management Bus (PMBus) Interface
        1. 6.19.3.1 PMBus Electrical Data and Timing
          1. 6.19.3.1.1 PMBus Electrical Characteristics
          2. 6.19.3.1.2 PMBus Fast Plus Mode Switching Characteristics
          3. 6.19.3.1.3 PMBus Fast Mode Switching Characteristics
          4. 6.19.3.1.4 PMBus Standard Mode Switching Characteristics
      4. 6.19.4 Serial Communications Interface (SCI)
      5. 6.19.5 Serial Peripheral Interface (SPI)
        1. 6.19.5.1 SPI Controller Mode Timings
          1. 6.19.5.1.1 SPI Controller Mode Timing Requirements
          2. 6.19.5.1.2 SPI Controller Mode Switching Characteristics - Clock Phase 0
          3. 6.19.5.1.3 SPI Controller Mode Switching Characteristics - Clock Phase 1
          4. 6.19.5.1.4 SPI Controller Mode Timing Diagrams
        2. 6.19.5.2 SPI Peripheral Mode Timings
          1. 6.19.5.2.1 SPI Peripheral Mode Timing Requirements
          2. 6.19.5.2.2 SPI Peripheral Mode Switching Characteristics
          3. 6.19.5.2.3 SPI Peripheral Mode Timing Diagrams
      6. 6.19.6 Local Interconnect Network (LIN)
      7. 6.19.7 Fast Serial Interface (FSI)
        1. 6.19.7.1 FSI Transmitter
          1. 6.19.7.1.1 FSITX Electrical Data and Timing
            1. 6.19.7.1.1.1 FSITX Switching Characteristics
            2. 6.19.7.1.1.2 FSITX Timings
        2. 6.19.7.2 FSI Receiver
          1. 6.19.7.2.1 FSIRX Electrical Data and Timing
            1. 6.19.7.2.1.1 FSIRX Timing Requirements
            2. 6.19.7.2.1.2 FSIRX Switching Characteristics
            3. 6.19.7.2.1.3 FSIRX Timings
        3. 6.19.7.3 FSI SPI Compatibility Mode
          1. 6.19.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.19.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.19.7.3.1.2 FSITX SPI Signaling Mode Timings
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 Memory Map
        1. 7.3.1.1 Dedicated RAM (Mx RAM)
        2. 7.3.1.2 Local Shared RAM (LSx RAM)
        3. 7.3.1.3 Global Shared RAM (GSx RAM)
        4. 7.3.1.4 Message RAM
      2. 7.3.2 Control Law Accelerator (CLA) Memory Map
      3. 7.3.3 Flash Memory Map
        1. 7.3.3.1 Addresses of Flash Sectors
      4. 7.3.4 Peripheral Registers Memory Map
    4. 7.4  Identification
    5. 7.5  Bus Architecture – Peripheral Connectivity
    6. 7.6  C28x Processor
      1. 7.6.1 Floating-Point Unit (FPU)
      2. 7.6.2 Trigonometric Math Unit (TMU)
      3. 7.6.3 VCRC Unit
    7. 7.7  Control Law Accelerator (CLA)
    8. 7.8  Embedded Real-Time Analysis and Diagnostic (ERAD)
    9. 7.9  Direct Memory Access (DMA)
    10. 7.10 Device Boot Modes
      1. 7.10.1 Device Boot Configurations
        1. 7.10.1.1 Configuring Boot Mode Pins
        2. 7.10.1.2 Configuring Boot Mode Table Options
      2. 7.10.2 GPIO Assignments
    11. 7.11 Security
      1. 7.11.1 Securing the Boundary of the Chip
        1. 7.11.1.1 JTAGLOCK
        2. 7.11.1.2 Zero-pin Boot
      2. 7.11.2 Dual-Zone Security
      3. 7.11.3 Disclaimer
    12. 7.12 Watchdog
    13. 7.13 C28x Timers
    14. 7.14 Dual-Clock Comparator (DCC)
      1. 7.14.1 Features
      2. 7.14.2 Mapping of DCCx Clock Source Inputs
    15. 7.15 Configurable Logic Block (CLB)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Typical Application
      1. 8.1.1 Reference Design
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Markings
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2.     TAPE AND REEL INFORMATION
    3.     TRAY

5.3.2 Digital Signals

Table 5-3 Digital Signals
SIGNAL NAME PIN TYPE DESCRIPTION GPIO 100 PZ 80 PNA 80 PN 64 PM 56 RSH 49 YAF 32 ZNG
ADCE_EXTMUXSEL0 O ADCE external mux selection pin for position 0 20, 228 14, 48 10, 33 10, 33 6, 27 24 A3, F6 7, 25
ADCE_EXTMUXSEL1 O ADCE external mux selection pin for position 1 21, 226 15, 49 11, 34 11, 34 7, 28 25 A3 7
ADCE_EXTMUXSEL2 O ADCE external mux selection pin for position 2 242 16 12 12 8 6 B4 6
ADCE_EXTMUXSEL3 O ADCE external mux selection pin for position 3 224 17 13 13 9 7 A4 5
ADCSOCAO O ADC Start of Conversion A for External ADC 8, 33, 53, 228 12, 14, 53, 74 10, 38, 58 10, 38, 58 6, 32, 47 29 A3 7
ADCSOCBO O ADC Start of Conversion B for External ADC 10, 32, 54 13, 64, 93 49, 76 49, 76 40, 63 37 F5 20
AUXCLKIN I Auxilary Clock Input 29 100 3 3 1 2
CLB_OUTPUTXBAR1 O CLB Output X-BAR Output 1 19, 22 69, 83 51, 67 51, 67 42, 56 39, 51 G3 17
CLB_OUTPUTXBAR2 O CLB Output X-BAR Output 2 7, 39, 47 6, 84 68 56, 68 57 52
CLB_OUTPUTXBAR3 O CLB Output X-BAR Output 3 23, 42, 44 81, 85 57, 65, 69 57, 65, 69 54 49
CLB_OUTPUTXBAR4 O CLB Output X-BAR Output 4 10, 40, 43, 45 80, 93 54, 64, 73, 76 54, 64, 73, 76 53, 63 48 D3
CLB_OUTPUTXBAR5 O CLB Output X-BAR Output 5 5, 8, 52 11, 74, 89 58, 74 58, 74 47, 61 55 C1 11
CLB_OUTPUTXBAR6 O CLB Output X-BAR Output 6 4, 15, 53 12, 75, 95 59, 78 59, 78 48 43 F2 16
CLB_OUTPUTXBAR7 O CLB Output X-BAR Output 7 1, 14, 56 65, 78, 96 62, 79 62, 79 51 46 F1 15
CLB_OUTPUTXBAR8 O CLB Output X-BAR Output 8 0, 6, 57 66, 79, 97 63, 80 63, 80 52, 64 1, 47 B1, E1 13
EPWM1_A O ePWM-1 Output A 0, 4, 30, 224 17, 75, 79, 98 1, 13, 59, 63 1, 13, 59, 63 9, 48, 52 7, 43, 47 A4, E1, F2 5, 13, 16
EPWM1_B O ePWM-1 Output B 1, 5, 31, 226 15, 78, 89, 99 2, 11, 62, 74 2, 11, 62, 74 7, 51, 61 46, 55 A3, C1, F1 7, 11, 15
EPWM2_A O ePWM-2 Output A 2, 6, 7, 41, 230 40, 77, 82, 84, 97 29, 61, 66, 68, 80 29, 61, 66, 68, 80 25, 50, 55, 57, 64 1, 23, 45, 50, 52 B1, C3, E6 9
EPWM2_B O ePWM-2 Output B 3, 7, 40, 227, 228 14, 38, 76, 80, 84 10, 28, 60, 64, 68 10, 28, 60, 64, 68 6, 24, 49, 53, 57 22, 44, 48, 52 A3, D3, E2, E6 7
EPWM3_A O ePWM-3 Output A 0, 4, 14, 227 38, 75, 79, 96 28, 59, 63, 79 28, 59, 63, 79 24, 48, 52 22, 43, 47 E1, E6, F2 13, 16
EPWM3_B O ePWM-3 Output B 1, 5, 15, 230 40, 78, 89, 95 29, 62, 74, 78 29, 62, 74, 78 25, 51, 61 23, 46, 55 C1, E6, F1 11, 15
EPWM4_A O ePWM-4 Output A 2, 6, 22, 242 16, 77, 83, 97 12, 61, 67, 80 12, 61, 67, 80 8, 50, 56, 64 1, 6, 45, 51 B1, B4 6
EPWM4_B O ePWM-4 Output B 3, 7, 23 76, 81, 84 60, 65, 68 60, 65, 68 49, 54, 57 44, 49, 52 E2
EPWM5_A O ePWM-5 Output A 8, 37 61, 74 46, 58 46, 58 37, 47 34 E5 22
EPWM5_B O ePWM-5 Output B 9, 35 63, 90 48, 75 48, 75 39, 62 36, 56 C2, G5 10, 21
EPWM6_A O ePWM-6 Output A 10, 17, 18, 226 15, 55, 68, 93 11, 40, 50, 76 11, 40, 50, 76 7, 34, 41, 63 31, 38 A3, G4 7, 18
EPWM6_B O ePWM-6 Output B 11, 19 52, 69 37, 51 37, 51 31, 42 28, 39 E3, G3 17
EPWM7_A O ePWM-7 Output A 12, 28, 41, 236 1, 39, 51, 82 4, 28, 36, 66 4, 28, 36, 66 2, 24, 30, 55 3, 22, 27, 50 C3 9
EPWM8_A O ePWM-8 Output A 14, 24 56, 96 3, 35 41, 79 35 32 G7 24
EPWM9_A O ePWM-9 Output A 16, 24 54, 56 39, 41 39, 41 33, 35 30, 32 G7 24
EPWM9_B O ePWM-9 Output B 17 55 40 40 34 31
EPWM10_A O ePWM-10 Output A 2, 62, 228 14, 46, 77 10, 31, 61 10, 31, 61 6, 50 45 A3 7
EPWM10_B O ePWM-10 Output B 1, 63, 226 15, 47, 78 11, 32, 62 11, 32, 62 7, 51 46 A3, F1 7, 15
EPWM11_A O ePWM-11 Output A 8, 242 16, 74 12, 58 12, 58 8, 47 6 B4 6
EPWM11_B O ePWM-11 Output B 4, 224 17, 75 13, 59 13, 59 9, 48 7, 43 A4, F2 5, 16
EPWM12_A O ePWM-12 Output A 20, 23, 236, 253 39, 41, 48, 81 28, 33, 65 28, 33, 65 24, 27, 54 22, 24, 49 F6 25
EPWM12_B O ePWM-12 Output B 21, 41, 60, 247 42, 44, 49, 82 34, 66 34, 66 28, 55 25, 50 C3 9
EQEP1_A I eQEP-1 Input A 6, 10, 20, 25, 28, 35, 40, 44, 50, 56, 224 1, 9, 17, 48, 57, 63, 65, 80, 85, 93, 97 4, 13, 33, 42, 48, 64, 69, 76, 80 4, 13, 33, 42, 48, 64, 69, 76, 80 2, 9, 27, 39, 53, 63, 64 1, 3, 7, 24, 36, 48 A4, B1, D3, F6, G5 5, 21, 25
EQEP1_B I eQEP-1 Input B 7, 11, 21, 29, 37, 41, 51, 57, 228 10, 14, 49, 52, 61, 66, 82, 84, 100 3, 10, 34, 37, 46, 66, 68 3, 10, 34, 37, 46, 66, 68 1, 6, 28, 31, 37, 55, 57 2, 25, 28, 34, 50, 52 A3, C3, E3, E5 7, 9, 22
EQEP1_INDEX I/O eQEP-1 Index 0, 9, 13, 17, 23, 31, 32, 39, 43, 53, 59, 236, 242 12, 16, 39, 50, 55, 64, 79, 81, 90, 92, 99 2, 12, 28, 35, 40, 49, 54, 63, 65, 75 2, 12, 28, 35, 40, 49, 54, 56, 63, 65, 75 8, 24, 29, 34, 40, 52, 54, 62 6, 22, 26, 31, 37, 47, 49, 56 B4, C2, E1, F5 6, 10, 13, 20
EQEP1_STROBE I/O eQEP-1 Strobe 1, 8, 12, 16, 22, 30, 42, 52, 58, 226 11, 15, 51, 54, 67, 74, 78, 83, 98 1, 11, 36, 39, 57, 58, 62, 67 1, 11, 36, 39, 57, 58, 62, 67 7, 30, 33, 47, 51, 56 27, 30, 46, 51 A3, F1 7, 15
EQEP2_A I eQEP-2 Input A 11, 14, 18, 24, 54 13, 52, 56, 68, 96 37, 41, 50, 79 37, 41, 50, 79 31, 35, 41 28, 32, 38 E3, G4, G7 18, 24
EQEP2_B I eQEP-2 Input B 15, 16, 19, 25, 33, 55 43, 53, 54, 57, 69, 95 38, 39, 42, 51, 78 38, 39, 42, 51, 78 32, 33, 42 29, 30, 39 G3 17
EQEP2_INDEX I/O eQEP-2 Index 26, 29, 39, 57 58, 66, 100 3, 43 3, 43, 56 1 2
EQEP2_STROBE I/O eQEP-2 Strobe 4, 27, 28, 56 1, 59, 65, 75 4, 44, 59 4, 44, 59 2, 48 3, 43 F2 16
EQEP3_B I eQEP-3 Input B 9, 26 58, 90 42, 67 43, 75 62 56 C2 10
EQEP3_INDEX I/O eQEP-3 Index 11, 18, 30 52, 68, 98 1, 37, 50 1, 37, 50 31, 41 28, 38 E3, G4 18
EQEP3_STROBE I/O eQEP-3 Strobe 10, 16, 27, 40 54, 59, 80, 93 39, 44, 64, 76 39, 44, 64, 76 33, 53, 63 30, 48 D3
ERRORSTS O Error Status Output. This signal requires an external pulldown. 24, 28, 29, 55 1, 43, 56, 100 3, 4, 41 3, 4, 41 1, 2, 35 2, 3, 32 G7 24
FSIRXA_CLK I FSIRX-A Input Clock 0, 4, 13, 30, 33, 39, 54, 57 13, 50, 53, 66, 75, 79, 98 1, 35, 38, 59, 63 1, 35, 38, 56, 59, 63 29, 32, 48, 52 26, 29, 43, 47 E1, F2 13, 16
FSIRXA_D0 I FSIRX-A Primary Data Input 3, 12, 32, 40, 44, 52, 58 11, 51, 64, 67, 76, 80, 85 36, 49, 60, 64, 69 36, 49, 60, 64, 69 30, 40, 49, 53 27, 37, 44, 48 D3, E2, F5 20
FSIRXA_D1 I FSIRX-A Optional Additional Data Input 2, 11, 31, 41, 53, 56 12, 52, 65, 77, 82, 99 2, 37, 61, 66 2, 37, 61, 66 31, 50, 55 28, 45, 50 C3, E3 9
FSITXA_CLK O FSITX-A Output Clock 7, 10, 27, 44, 51 10, 59, 84, 85, 93 44, 68, 69, 76 44, 68, 69, 76 57, 63 52
FSITXA_D0 O FSITX-A Primary Data Output 6, 9, 26, 45, 49 8, 58, 90, 97 43, 73, 75, 80 43, 73, 75, 80 62, 64 1, 56 B1, B3, C2 10
FSITXA_D1 O FSITX-A Optional Additional Data Output 5, 6, 8, 25, 46, 50 9, 57, 74, 89, 97 6, 42, 58, 74, 80 6, 42, 58, 74, 80 47, 61, 64 1, 55 B1, C1 11
GPIO0 I/O General-Purpose Input Output 0 0 79 63 63 52 47 E1 13
GPIO1 I/O General-Purpose Input Output 1 1 78 62 62 51 46 F1 15
GPIO2 I/O General-Purpose Input Output 2 2 77 61 61 50 45
GPIO3 I/O General-Purpose Input Output 3 3 76 60 60 49 44 E2
GPIO4 I/O General-Purpose Input Output 4 4 75 59 59 48 43 F2 16
GPIO5 I/O General-Purpose Input Output 5 5 89 74 74 61 55 C1 11
GPIO6 I/O General-Purpose Input Output 6 6 97 80 80 64 1 B1
GPIO7 I/O General-Purpose Input Output 7 7 84 68 68 57 52
GPIO8 I/O General-Purpose Input Output 8 8 74 58 58 47
GPIO9 I/O General-Purpose Input Output 9 9 90 75 75 62 56 C2 10
GPIO10 I/O General-Purpose Input Output 10 10 93 76 76 63
GPIO11 I/O General-Purpose Input Output 11 11 52 37 37 31 28 E3
GPIO12 I/O General-Purpose Input Output 12 12 51 36 36 30 27
GPIO13 I/O General-Purpose Input Output 13 13 50 35 35 29 26
GPIO14 I/O General-Purpose Input Output 14 14 96 79 79
GPIO15 I/O General-Purpose Input Output 15 15 95 78 78
GPIO16 I/O General-Purpose Input Output 16 16 54 39 39 33 30
GPIO17 I/O General-Purpose Input Output 17 17 55 40 40 34 31
GPIO18 I/O General-Purpose Input Output 18 18 68 50 50 41 38 G4 18
GPIO19 I/O General-Purpose Input Output 19 19 69 51 51 42 39 G3 17
GPIO20 I/O General-Purpose Input Output 20 20 48 33 33 27 24 F6 25
GPIO21 I/O General-Purpose Input Output 21 21 49 34 34 28 25
GPIO22 I/O General-Purpose Input Output 22 22 83 67 67 56 51
GPIO23 I/O General-Purpose Input Output 23 23 81 65 65 54 49
GPIO24 I/O General-Purpose Input Output 24 24 56 41 41 35 32 G7 24
GPIO25 I/O General-Purpose Input Output 25 25 57 42 42
GPIO26 I/O General-Purpose Input Output 26 26 58 43 43
GPIO27 I/O General-Purpose Input Output 27 27 59 44 44
GPIO28 I/O General-Purpose Input Output 28 28 1 4 4 2 3
GPIO29 I/O General-Purpose Input Output 29 29 100 3 3 1 2
GPIO30 I/O General-Purpose Input Output 30 30 98 1 1
GPIO31 I/O General-Purpose Input Output 31 31 99 2 2
GPIO32 I/O General-Purpose Input Output 32 32 64 49 49 40 37 F5 20
GPIO33 I/O General-Purpose Input Output 33 33 53 38 38 32 29
GPIO34 I/O General-Purpose Input Output 34 34 94 77 77
GPIO35 I/O General-Purpose Input Output 35 35 63 48 48 39 36 G5 21
GPIO37 I/O General-Purpose Input Output 37 37 61 46 46 37 34 E5 22
GPIO39 I/O General-Purpose Input Output 39 39 56 56
GPIO40 I/O General-Purpose Input Output 40 40 80 64 64 53 48 D3
GPIO41 I/O General-Purpose Input Output 41 41 82 66 66 55 50 C3 9
GPIO42 I/O General-Purpose Input Output 42 42 57 57
GPIO43 I/O General-Purpose Input Output 43 43 54 54
GPIO44 I/O General-Purpose Input Output 44 44 85 69 69
GPIO45 I/O General-Purpose Input Output 45 45 73 73
GPIO46 I/O General-Purpose Input Output 46 46 6 6
GPIO47 I/O General-Purpose Input Output 47 47 6
GPIO48 I/O General-Purpose Input Output 48 48 7 B2
GPIO49 I/O General-Purpose Input Output 49 49 8 B3
GPIO50 I/O General-Purpose Input Output 50 50 9
GPIO51 I/O General-Purpose Input Output 51 51 10
GPIO52 I/O General-Purpose Input Output 52 52 11
GPIO53 I/O General-Purpose Input Output 53 53 12
GPIO54 I/O General-Purpose Input Output 54 54 13
GPIO55 I/O General-Purpose Input Output 55 55 43
GPIO56 I/O General-Purpose Input Output 56 56 65
GPIO57 I/O General-Purpose Input Output 57 57 66
GPIO58 I/O General-Purpose Input Output 58 58 67
GPIO59 I/O General-Purpose Input Output 59 59 92
GPIO60 I/O General-Purpose Input Output 60 60 44
GPIO61 I/O General-Purpose Input Output 61 61 91
GPIO62 I/O General-Purpose Input Output 62 62 46 31 31
GPIO63 I/O General-Purpose Input Output 63 63 47 32 32
GPIO224 I/O General-Purpose Input Output 224 224 17 13 13 9 7 A4 5
GPIO226 I/O General-Purpose Input Output 226 226 15 11 11 7 A3 7
GPIO227 I/O General-Purpose Input Output 227 227 38 28 28 24 22 E6
GPIO228 I/O General-Purpose Input Output 228 228 14 10 10 6 A3 7
GPIO230 I/O General-Purpose Input Output 230 230 40 29 29 25 23 E6
GPIO236 I/O General-Purpose Input Output 236 236 39 28 28 24 22
GPIO242 I/O General-Purpose Input Output 242 242 16 12 12 8 6 B4 6
GPIO247 I/O General-Purpose Input Output 247 247 42
GPIO253 I/O General-Purpose Input Output 253 253 41
I2CA_SCL I/OD I2C-A Open-Drain Bidirectional Clock 1, 4, 8, 9, 18, 20, 27, 33, 37, 43, 57 48, 53, 59, 61, 66, 68, 74, 75, 78, 90 33, 38, 44, 46, 50, 54, 58, 59, 62, 75 33, 38, 44, 46, 50, 54, 58, 59, 62, 75 27, 32, 37, 41, 47, 48, 51, 62 24, 29, 34, 38, 43, 46, 56 C2, E5, F1, F2, F6, G4 10, 15, 16, 18, 22, 25
I2CA_SDA I/OD I2C-A Open-Drain Bidirectional Data 0, 5, 10, 19, 21, 26, 32, 35, 42, 56, 230 40, 49, 58, 63, 64, 65, 69, 79, 89, 93 29, 34, 43, 48, 49, 51, 57, 63, 74, 76 29, 34, 43, 48, 49, 51, 57, 63, 74, 76 25, 28, 39, 40, 42, 52, 61, 63 23, 25, 36, 37, 39, 47, 55 C1, E1, E6, F5, G3, G5 11, 13, 17, 20, 21, UNBONDED
I2CB_SCL I/OD I2C-B Open-Drain Bidirectional Clock 3, 9, 15, 29, 51, 227 10, 38, 76, 90, 95, 100 3, 28, 60, 75, 78 3, 28, 60, 75, 78 1, 24, 49, 62 2, 22, 44, 56 C2, E2, E6 10
I2CB_SDA I/OD I2C-B Open-Drain Bidirectional Data 2, 14, 28, 34, 50, 230 1, 9, 40, 77, 94, 96 4, 29, 61, 77, 79 4, 29, 61, 77, 79 2, 25, 50 3, 23, 45 E6
LINA_RX I LIN-A Receive 9, 11, 13, 15, 19, 23, 29, 33, 35, 41, 42, 47, 49, 55, 59, 63, 226 6, 8, 15, 43, 47, 50, 52, 53, 63, 69, 81, 82, 90, 92, 95, 100 3, 11, 32, 35, 37, 38, 48, 51, 57, 65, 66, 75, 78 3, 11, 32, 35, 37, 38, 48, 51, 57, 65, 66, 75, 78 1, 7, 29, 31, 32, 39, 42, 54, 55, 62 2, 26, 28, 29, 36, 39, 49, 50, 56 A3, B3, C2, C3, E3, G3, G5 7, 9, 10, 17, 21
LINA_TX O LIN-A Transmit 10, 12, 14, 18, 22, 24, 28, 32, 37, 40, 44, 46, 54, 58 1, 13, 51, 56, 61, 64, 67, 68, 80, 83, 85, 93, 96 4, 6, 36, 41, 46, 49, 50, 64, 67, 69, 76, 79 4, 6, 36, 41, 46, 49, 50, 64, 67, 69, 76, 79 2, 30, 35, 37, 40, 41, 53, 56, 63 3, 27, 32, 34, 37, 38, 48, 51 D3, E5, F5, G4, G7 18, 20, 22, 24
MCANA_RX I CAN/CAN FD Receive 0, 5, 11, 12, 21, 30, 39, 47, 49, 51, 57, 61, 63, 230, 242 6, 8, 10, 16, 40, 47, 49, 51, 52, 66, 79, 89, 91, 98 1, 12, 29, 32, 34, 36, 37, 56, 63, 74 1, 12, 29, 32, 34, 36, 37, 56, 63, 74 8, 25, 28, 30, 31, 52, 61 6, 23, 25, 27, 28, 47, 55 B3, B4, C1, E1, E3, E6 6, 11, 13
MCANA_TX O CAN/CAN FD Transmit 1, 4, 7, 13, 17, 20, 31, 46, 48, 50, 56, 60, 62, 224, 228 7, 9, 14, 17, 44, 46, 48, 50, 55, 65, 75, 78, 84, 99 2, 6, 10, 13, 31, 33, 35, 40, 59, 62, 68 2, 6, 10, 13, 31, 33, 35, 40, 59, 62, 68 6, 9, 27, 29, 34, 48, 51, 57 7, 24, 26, 31, 43, 46, 52 A3, A4, B2, F1, F2, F6 5, 7, 15, 16, 25
OUTPUTXBAR1 O Output X-BAR Output 1 2, 24, 34, 58, 227 38, 56, 67, 77, 94 28, 41, 61, 77 28, 41, 61, 77 24, 35, 50 22, 32, 45 E6, G7 24
OUTPUTXBAR2 O Output X-BAR Output 2 3, 25, 37, 54, 59, 242 13, 16, 57, 61, 76, 92 12, 42, 46, 60 12, 42, 46, 60 8, 37, 49 6, 34, 44 B4, E2, E5 6, 22
OUTPUTXBAR3 O Output X-BAR Output 3 4, 5, 14, 26, 48, 55, 60, 62, 224 7, 17, 43, 44, 46, 58, 75, 89, 96 13, 31, 43, 59, 74, 79 13, 31, 43, 59, 74, 79 9, 48, 61 7, 43, 55 A4, B2, C1, F2 5, 11, 16
OUTPUTXBAR4 O Output X-BAR Output 4 6, 15, 27, 33, 49, 61, 63 8, 47, 53, 59, 91, 95, 97 32, 38, 44, 78, 80 32, 38, 44, 78, 80 32, 64 1, 29 B1, B3
OUTPUTXBAR5 O Output X-BAR Output 5 7, 28, 42 1, 84 4, 57, 68 4, 57, 68 2, 57 3, 52
OUTPUTXBAR6 O Output X-BAR Output 6 9, 29, 43 90, 100 3, 54, 75 3, 54, 75 1, 62 2, 56 C2 10
OUTPUTXBAR7 O Output X-BAR Output 7 0, 11, 16, 30, 44 52, 54, 79, 85, 98 1, 37, 39, 63, 69 1, 37, 39, 63, 69 31, 33, 52 28, 30, 47 E1, E3 13
OUTPUTXBAR8 O Output X-BAR Output 8 17, 31, 45 55, 99 2, 40, 73 2, 40, 73 34 31
PMBUSA_ALERT I/OD PMBus-A Open-Drain Bidirectional Alert Signal 13, 19, 27, 37, 43, 45 50, 59, 61, 69 35, 44, 46, 51, 54, 73 35, 44, 46, 51, 54, 73 29, 37, 42 26, 34, 39 E5, G3 17, 22
PMBUSA_CTL I/O PMBus-A Control Signal - Target Input/Controller Output 12, 18, 26, 35, 42, 44 51, 58, 63, 68, 85 36, 43, 48, 50, 57, 69 36, 43, 48, 50, 57, 69 30, 39, 41 27, 36, 38 G4, G5 18, 21
PMBUSA_SCL I/OD PMBus-A Open-Drain Bidirectional Clock 3, 9, 15, 16, 24, 35, 41, 47, 230 6, 40, 54, 56, 63, 76, 82, 90, 95 29, 39, 41, 48, 60, 66, 75, 78 29, 39, 41, 48, 60, 66, 75, 78 25, 33, 35, 39, 49, 55, 62 23, 30, 32, 36, 44, 50, 56 C2, C3, E2, E6, G5, G7 9, 10, 21, 24
PMBUSA_SDA I/OD PMBus-A Open-Drain Bidirectional Data 2, 14, 17, 25, 32, 34, 40, 44, 46, 48, 62 7, 46, 55, 57, 64, 77, 80, 85, 94, 96 6, 31, 40, 42, 49, 61, 64, 69, 77, 79 6, 31, 40, 42, 49, 61, 64, 69, 77, 79 34, 40, 50, 53 31, 37, 45, 48 B2, D3, F5 20
SCIA_RX I SCI-A Receive Data 0, 3, 5, 9, 17, 25, 28, 35, 49, 63 1, 8, 47, 55, 57, 63, 76, 79, 89, 90 4, 32, 40, 42, 48, 60, 63, 74, 75 4, 32, 40, 42, 48, 60, 63, 74, 75 2, 34, 39, 49, 52, 61, 62 3, 31, 36, 44, 47, 55, 56 B3, C1, C2, E1, E2, G5 10, 11, 13, 21
SCIA_TX O SCI-A Transmit Data 1, 2, 7, 8, 16, 24, 29, 37, 48, 62 7, 46, 54, 56, 61, 74, 77, 78, 84, 100 3, 31, 39, 41, 46, 58, 61, 62, 68 3, 31, 39, 41, 46, 58, 61, 62, 68 1, 33, 35, 37, 47, 50, 51, 57 2, 30, 32, 34, 45, 46, 52 B2, E5, F1, G7 15, 22, 24
SCIB_RX I SCI-B Receive Data 11, 13, 15, 19, 23, 41, 57 50, 52, 66, 69, 81, 82, 95 35, 37, 51, 65, 66, 78 35, 37, 51, 65, 66, 78 29, 31, 42, 54, 55 26, 28, 39, 49, 50 C3, E3, G3 9, 17
SCIB_TX O SCI-B Transmit Data 9, 10, 12, 14, 18, 22, 40, 56 51, 65, 68, 80, 83, 90, 93, 96 36, 50, 64, 67, 75, 76, 79 36, 50, 64, 67, 75, 76, 79 30, 41, 53, 56, 62, 63 27, 38, 48, 51, 56 C2, D3, G4 10, 18
SCIC_RX I SCI-C Receive Data 21, 33, 42, 226 15, 49, 53 11, 34, 38, 57 11, 34, 38, 57 7, 28, 32 25, 29 A3 7
SCIC_TX O SCI-C Transmit Data 20, 43, 224 17, 48 13, 33, 54 13, 33, 54 9, 27 7, 24 A4, F6 5, 25
SD1_C1 I SDFM-1 Channel 1 Clock Input 17, 33, 49, 53 8, 12, 23, 53, 55 19, 38, 40 19, 38, 40 15, 32, 34 13, 29, 31 B3, C6 1
SD1_C2 I SDFM-1 Channel 2 Clock Input 19, 33, 51, 54 10, 13, 31, 53, 69 23, 38, 51 23, 38, 51 19, 32, 42 17, 29, 39 D6, G3 17, 28
SD1_C3 I SDFM-1 Channel 3 Clock Input 21, 53, 55, 227 12, 38, 43, 49 28, 34 28, 34 24, 28 22, 25 E6
SD1_C4 I SDFM-1 Channel 4 Clock Input 23, 55, 56, 230 40, 43, 65, 81 29, 65 29, 65 25, 54 23, 49 E6
SD1_D1 I SDFM-1 Channel 1 Data Input 16, 48 7, 19, 54 15, 39 15, 39 11, 33 9, 30 B2, C4 4
SD1_D2 I SDFM-1 Channel 2 Data Input 18, 32, 50 9, 20, 64, 68 16, 49, 50 16, 49, 50 12, 40, 41 10, 37, 38 A6, F5, G4 2, 18, 20
SD1_D3 I SDFM-1 Channel 3 Data Input 20, 52 11, 21, 48 17, 33 17, 33 13, 27 11, 24 C5, F6 2, 25
SD1_D4 I SDFM-1 Channel 4 Data Input 22, 54 13, 22, 83 18, 67 18, 67 14, 56 12, 51 B5 3
SD2_C1 I SDFM-2 Channel 1 Clock Input 25, 35, 57, 228 14, 37, 57, 63, 66 10, 24, 42, 48 10, 24, 42, 48 6, 20, 39 18, 36 A3, B7, G5 7, 21, 28
SD2_C2 I SDFM-2 Channel 2 Clock Input 27, 58, 59 36, 59, 67, 92 27, 44 27, 44 23 21 E7 26
SD2_C3 I SDFM-2 Channel 3 Clock Input 29, 45, 59, 61 28, 91, 92, 100 3, 22, 73 3, 22, 73 1, 18 2, 16 D5 27
SD2_C4 I SDFM-2 Channel 4 Clock Input 31, 46, 60 32, 44, 99 2, 6 2, 6
SD2_D1 I SDFM-2 Channel 1 Data Input 24, 49, 56 8, 56, 65 14, 41 14, 41 10, 35 8, 32 A5, B3, G7 4, 24
SD2_D2 I SDFM-2 Channel 2 Data Input 26, 50, 58, 242 9, 16, 58, 67 12, 43 12, 43 8 6 B4 6
SD2_D3 I SDFM-2 Channel 3 Data Input 28, 43, 51, 60, 224 1, 10, 17, 44 4, 13, 54 4, 13, 54 2, 9 3, 7 A4 5
SD2_D4 I SDFM-2 Channel 4 Data Input 30, 47, 52, 226 6, 11, 15, 98 1, 11 1, 11 7 A3 7
SPIA_CLK I/O SPI-A Clock 3, 9, 12, 18, 56, 226 15, 51, 65, 68, 76, 90 11, 36, 50, 60, 75 11, 36, 50, 60, 75 7, 30, 41, 49, 62 27, 38, 44, 56 A3, C2, E2, G4 7, 10, 18
SPIA_PICO I/O SPI-A Peripheral In, Controller Out (PICO) 2, 8, 11, 16, 54, 224 13, 17, 52, 54, 74, 77 13, 37, 39, 58, 61 13, 37, 39, 58, 61 9, 31, 33, 47, 50 7, 28, 30, 45 A4, E3 5
SPIA_POCI I/O SPI-A Peripheral Out, Controller In (POCI) 1, 4, 10, 13, 17, 35, 55, 228 14, 43, 50, 55, 63, 75, 78, 93 10, 35, 40, 48, 59, 62, 76 10, 35, 40, 48, 59, 62, 76 6, 29, 34, 39, 48, 51, 63 26, 31, 36, 43, 46 A3, F1, F2, G5 7, 15, 16, 21
SPIA_PTE I/O SPI-A Peripheral Transmit Enable (PTE) 0, 5, 11, 19, 24, 37, 57, 242 16, 52, 56, 61, 66, 69, 79, 89 12, 37, 41, 46, 51, 63, 74 12, 37, 41, 46, 51, 63, 74 8, 31, 35, 37, 42, 52, 61 6, 28, 32, 34, 39, 47, 55 B4, C1, E1, E3, E5, G3, G7 6, 11, 13, 17, 22, 24
SPIB_CLK I/O SPI-B Clock 4, 14, 22, 26, 28, 32, 52, 58 1, 11, 58, 64, 67, 75, 83, 96 4, 43, 49, 59, 67, 79 4, 43, 49, 59, 67, 79 2, 40, 48, 56 3, 37, 43, 51 F2, F5 16, 20
SPIB_PICO I/O SPI-B Peripheral In, Controller Out (PICO) 7, 20, 24, 30, 40, 50, 56, 60 9, 44, 48, 56, 65, 80, 84, 98 1, 33, 41, 64, 68 1, 33, 41, 64, 68 27, 35, 53, 57 24, 32, 48, 52 D3, F6, G7 24, 25
SPIB_POCI I/O SPI-B Peripheral Out, Controller In (POCI) 6, 16, 21, 25, 31, 41, 51, 57, 61 10, 49, 54, 57, 66, 82, 91, 97, 99 2, 34, 39, 42, 66, 80 2, 34, 39, 42, 66, 80 28, 33, 55, 64 1, 25, 30, 50 B1, C3 9
SPIB_PTE I/O SPI-B Peripheral Transmit Enable (PTE) 15, 23, 27, 29, 33, 53, 59 12, 53, 59, 81, 92, 95, 100 3, 38, 44, 65, 78 3, 38, 44, 65, 78 1, 32, 54 2, 29, 49
SYNCOUT O External ePWM Synchronization Pulse 6, 39, 52 11, 97 56, 80 56, 80 64 1 B1
TDI I JTAG Test Data Input (TDI) - TDI is the default mux selection for the pin. The internal pullup is disabled by default. The internal pullup should be enabled or an external pullup added on the board if this pin is used as JTAG TDI to avoid a floating input. 35 63 48 48 39 36 G5 21
TDO O JTAG Test Data Output (TDO) - TDO is the default mux selection for the pin. The internal pullup is disabled by default. The TDO function will be in a tristate condition when there is no JTAG activity, leaving this pin floating; the internal pullup should be enabled or an external pullup added on the board to avoid a floating GPIO input. 37 61 46 46 37 34 E5 22
X1 I/O Crystal oscillator input or single-ended clock input. The device initialization software must configure this pin before the crystal oscillator is enabled. To use this oscillator, a quartz crystal circuit must be connected to X1 and X2. This pin can also be used to feed a single-ended 3.3-V level clock. 19 69 51 51 42 39 G3 17
X2 I/O Crystal oscillator output. 18 68 50 50 41 38 G4 18
XCLKOUT O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device. 16, 18 54, 68 39, 50 39, 50 33, 41 30, 38 G4 18