SPRUJ59A April   2024  – September 2024 TMS320F28P550SG , TMS320F28P550SJ , TMS320F28P559SG-Q1 , TMS320F28P559SJ-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between F28003x and F28P55x
    1. 1.1 F28003x and F28P55x Feature Comparison
  5. 2PCB Hardware Changes
    1. 2.1 PCB Hardware Changes for the 100-Pin PZ, 80-Pin PNA and 64-Pin PM Packages
    2. 2.2 100-Pin PZ, 80-Pin PNA and 64-Pin PM Migration Between F28003x and F28P55x For New and Existing PCB
    3. 2.3 GPIO Input Buffer Control Register
  6. 3Feature Differences for System Consideration
    1. 3.1 New Features in F28P55x
      1. 3.1.1 Programmable Gain Amplifier(PGA)
      2. 3.1.2 Universal Serial Bus (USB)
      3. 3.1.3 5V Failsafe IOs
      4. 3.1.4 Flash Write Protection
      5. 3.1.5 Neural-Network Processing Unit (NPU)
    2. 3.2 Communication Module Changes
    3. 3.3 Control Module Changes
    4. 3.4 Analog Module Differences
    5. 3.5 Other Device Changes
      1. 3.5.1 PLL
      2. 3.5.2 PIE Channel Mapping
      3. 3.5.3 Bootrom
      4. 3.5.4 SW Libraries Included in the ROM
      5. 3.5.5 AGPIO
    6. 3.6 Power Management
      1. 3.6.1 LDO/VREG
      2. 3.6.2 POR/BOR
      3. 3.6.3 Power Consumption
    7. 3.7 Memory Module Changes
    8. 3.8 GPIO Multiplexing Changes
    9. 3.9 Analog Multiplexing Changes
  7. 4Application Code Migration From F28003x to F28P55x
    1. 4.1 C2000Ware Header Files
    2. 4.2 Linker Command Files
    3. 4.3 C2000Ware Examples
  8. 5Specific Use Cases Related to F28P55x New Features
    1. 5.1 PGA
    2. 5.2 USB
  9. 6EABI Support
    1. 6.1 Flash API
  10. 7References
  11. 8Revision History

3.7 Memory Module Changes

RAM and FLASH memories in F28003x and F28P55x devices have some similarities and differences. Table 3-10 summarizes the memory features including error-checking and security assignment.

Table 3-10 RAM and FLASH memory changes
Memory F28003x F28P55x
Size Parity/
ECC		 Secured Size Parity/
ECC		 Secured
RAM Dedicated(M0,M1) 4KB ECC No 4KB ECC No
Local Shared(LS0-LS7) 32KB ECC DCSM-
controlled		 32KB Parity DCSM-
controlled
Local Shared(LS8-LS9) - - - 32KB Parity DCSM-
controlled
Global Shared(GS0-GS3) 32KB ECC No 64KB Parity No
Message 512B(CPU-CLA)
512B(CLA-DMA)		 ECC No 512B(CPU-CLA)
512B(CLA-DMA)		 Parity No
Total RAM 69KB 133KB
FLASH Per Sector 8KB - - 2KB - -
Per Bank 128KB(3 banks) ECC DCSM-
controlled		 256KB(4 banks)
64KB(1 bank)		 ECC DCSM-
controlled
Total FLASH 384KB(3 banks) 1088KB(5 banks)