SPRUJ86B October   2023  – May 2024 AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
      1.      Preface: Read This First
        1. 1.1.1.1 Sitara MCU+ Academy
        2. 1.1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
    3. 1.3 Device Information
      1. 1.3.1 HSEC 180-pin Control Card Docking Station
      2. 1.3.2 Security
  6. 2Hardware
    1. 2.1  Component Identification
    2. 2.2  Power Requirements
      1. 2.2.1 Power Input Using USB Type-C Connector
      2. 2.2.2 Power Status LEDs
      3. 2.2.3 Power Tree
      4. 2.2.4 Power Sequence
      5. 2.2.5 PMIC
    3. 2.3  Functional Block Diagram
    4. 2.4  Reset
    5. 2.5  Clock
    6. 2.6  Boot Mode Selection
    7. 2.7  JTAG Path Selection
    8. 2.8  Header Information
    9. 2.9  GPIO Mapping
    10. 2.10 Push Buttons
    11. 2.11 Interfaces
      1. 2.11.1  Memory Interface
        1. 2.11.1.1 OSPI/QSPI
        2. 2.11.1.2 Board ID EEPROM
      2. 2.11.2  Ethernet Interface
        1. 2.11.2.1 Control Card Ethernet Routing
        2. 2.11.2.2 On Board Ethernet PHY
        3. 2.11.2.3 LED Indication in RJ45 Connector
      3. 2.11.3  I2C
      4. 2.11.4  Industrial Application LEDs
      5. 2.11.5  SPI
      6. 2.11.6  UART
      7. 2.11.7  MCAN
      8. 2.11.8  FSI
      9. 2.11.9  JTAG
      10. 2.11.10 Test Automation Header
      11. 2.11.11 LIN
      12. 2.11.12 MMC
      13. 2.11.13 ADC and DAC
    12. 2.12 HSEC Pinout and Pinmux Mapping
  7. 3Hardware Design Files
  8. 4Additional Information
    1. 4.1 If You Need Assistance
    2. 4.2 Trademarks
  9. 5Related Documentation
    1. 5.1 Supplemental Content
      1.      5.1.A E1 Board Modifications
      2.      5.1.B E2 Design Changes
  10. 6References
    1. 6.1 Reference Documents
    2. 6.2 Other TI Components Used in This Design
  11. 7Revision History
  12. 8Revision History

Boot Mode Selection

The bootmode for the AM263Px is selected by a DIP switch (SW6) or the test automation header. The test automation header uses an I2C IO expansion buffer to drive the bootmode when PORz is toggled. The supported boot modes are as shown in Table 3-4.

Table 2-4 Supported Boot Modes
Boot Mode/Peripheral Boot Media/Host Notes
QSPI(4S), 50MHz Flash Memory ROM configures OSPI controller in QSPI 4S mode and downloads image from external flash, supports UART fallback boot mode if any failures.
UART External Host ROM configures UART0 with baud rate of 115200bps and downloads image from external PC terminal using x-modem protocol.
QSPI(1S), 50MHz Flash Memory ROM configures OSPI controller in QSPI 1S mode and downloads image from external flash, supports UART fallback boot mode if any failures.
OSPI(8S), 50MHz Flash Memory ROM configures OSPI controller in 8S mode and downloads image from external flash, supports UART fallback boot mode if any failures.
xSPI (1S->8D) , 25MHz, SFDP QSPI Flash / External Host ROM configures OSPI controller in xSPI 8D mode ,Reads SFDP table for read command and downloads image from external flash, Flashes with SFDP are of JEDEC standard Rev D only supported.
DevBoot N/A No SBL. Used for development purposes only.
AM263P1, AM263P1-Q1, AM263P2, AM263P2-Q1, AM263P4, AM263P4-Q1 SW6 Switch Positions Figure 2-15 SW6 Switch Positions
Table 2-5 Boot-Mode Selection Table
Boot Mode SPI0_D0_pad (SOP3) SPI0_CLK_pad (SOP2) OSPI_D1 (SOP1) OSPI_D0 (SOP0)
QSPI(4S), 50MHz 0 0 0 0
UART 0 0 0 1
QSPI(1S), 50MHz 0 0 1 0
OSPI(8S), 50MHz 0 0 1 1
xSPI (1S->8D) , 25MHz, SFDP 1 1 0 0
DevBoot 1 0 1 1
Unsupported Boot Mode All other combinations not defined above.