SPRUJG2A December   2024  – September 2026 AM62D-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5. 1.5 EVM Revisions and Assembly Variants
  7. 2Hardware
    1. 2.1  Additional Images
    2. 2.2  Key Features
      1. 2.2.1 Processor
      2. 2.2.2 Power Supply
      3. 2.2.3 Memory
      4. 2.2.4 JTAG/Emulator
      5. 2.2.5 Supported Interfaces and Peripherals
      6. 2.2.6 Expansion Connectors/Headers to Support Application Specific Add‐On Boards
    3. 2.3  Power Requirements
    4. 2.4  Setup and Configuration
      1. 2.4.1 EVM DIP Switches
      2. 2.4.2 Boot Modes
      3. 2.4.3 User Test LEDs
    5. 2.5  Power ON/OFF Procedures
      1. 2.5.1 Power ON Procedure
      2. 2.5.2 Power OFF Procedure
      3. 2.5.3 Power Test Points
      4. 2.5.4 Power Indication LED
    6. 2.6  Interfaces
      1. 2.6.1  AM62D Audio EVM Interface Mapping
      2. 2.6.2  Audio Interface
        1. 2.6.2.1 Audio Stereo Lineouts
        2. 2.6.2.2 Audio Microphone and Line In
      3. 2.6.3  JTAG Interface
      4. 2.6.4  UART Interface
      5. 2.6.5  USB Interface
        1. 2.6.5.1 USB2.0 Type-A Interface
        2. 2.6.5.2 USB2.0 Type-C Interface
      6. 2.6.6  MCAN Interface
      7. 2.6.7  Memory Interfaces
        1. 2.6.7.1 LPDDR4 Interface
        2. 2.6.7.2 Octal Serial Peripheral Interface (OSPI)
        3. 2.6.7.3 MMC Interfaces
          1. 2.6.7.3.1 MMC0 - eMMC Interface
          2. 2.6.7.3.2 MMC1 - MicroSD Interface
        4. 2.6.7.4 Board ID EEPROM
      8. 2.6.8  Ethernet Interface
      9. 2.6.9  CPSW Ethernet 1 and CPSW Ethernet 2
      10. 2.6.10 GPIO Port Expander
      11. 2.6.11 GPIO Mapping
    7. 2.7  Power
      1. 2.7.1 Power Input
      2. 2.7.2 Power Supply
      3. 2.7.3 Power Sequencing
      4. 2.7.4 AM62D SOC Power
      5. 2.7.5 Current Monitoring
    8. 2.8  Clocking
      1. 2.8.1 Peripheral Ref Clock
    9. 2.9  Reset
    10. 2.10 CPLD Mapping
    11. 2.11 Audio Expansion Connectors (Headers)
      1. 2.11.1 Audio Expansion Connector 1
      2. 2.11.2 Audio Expansion Connector 2
    12. 2.12 Interrupt
    13. 2.13 I2C Address Mapping
  8. 3Hardware Design Files
  9. 4Compliance Information
    1. 4.1 Compliance and Certifications
  10. 5Additional Information
    1. 5.1 Known Hardware or Software Issues
      1. 5.1.1 Issue 1 - CPLD C4 Version Unavailable
      2. 5.1.2 Issue 2 - RGMII Boot Failure
    2. 5.2 Trademarks
  11. 6Related Documentation
  12. 7References
  13. 8Revision History

2.4.2 Boot Modes

The boot mode for the EVM board is defined by two banks of switches SW1 and SW2. This allows for AM62D SoC Boot mode control by either the user (DIP Switch Control).

All the bits of switch (SW1 and SW2) have a weak pull down resistor and a strong pull up resistor as shown in Figure 2-4. Note that OFF setting provides a low logic level (‘0’) and an ON setting provide a high logic level (‘1’).

AUDIO-AM62D-EVM Boot Mode Switch (MMCSD Boot) Figure 2-4 Boot Mode Switch (MMCSD Boot)

The boot mode pins of the SoC have associated alternate functions during normal operation. Hence isolation is provided using Buffer ICs to cater for alternate pin functionality. The output of the buffer is connected to the boot mode pins on the AM62D SoC and the output is enabled only when the boot mode is needed during a reset cycle.

The input to the buffer is connected to the DIP switch circuit and to the output of an I2C I/O Expander set by the test automation circuit. If the test automation circuit controls the boot mode, manually set all the switches to the OFF position. The boot mode buffer is powered by an always ON power supply so that the boot mode remains present even if the SoC is power cycled.

Switch SW1 and SW2 bits [15:0] are used to set the SoC boot mode.

The switch map to the boot mode functions is provided in the following tables.

Table 2-3 BOOTMODE Pin Mapping
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Reserved Reserved Backup Boot Mode Configuration Backup Boot Mode Primary Boot Mode Configuration Primary Boot Mode PLL Configuration
  • BOOTMODE [2:0] – Denote system clock frequency for PLL configuration.
    • Table 2-4 gives details on PLL reference clock selection.
  • BOOTMODE [6:3] – This provides primary boot mode configuration to select the requested boot mode after POR, that is, the peripheral/memory to boot from primary boot device selection details.
    • Table 2-5 gives the primary boot mode configuration details.
  • BOOTMODE [9:7] – These pins provide optional settings and are used in conjunction with the primary boot device selected.
    • Table 2-6 gives primary boot media configuration details.
  • BOOTMODE [12:10] – Select the backup boot mode, that is, the peripheral/memory to boot from, if primary boot device failed.
    • Table 2-7 provides backup boot mode selection details.
  • BOOTMODE [13] – These pins provide optional settings and are used in conjunction with the backup boot device. Switch SW1.6 when ON sets 1 and sets 0 if OFF, see the device-specific TRM.
  • BOOTMODE [15:14] – Reserved. Provides backup boot media configuration options.
Table 2-4 PLL Reference Clock Selection BOOTMODE [2:0]
SW2.3 (B2) SW2.2 (B1) SW2.1 (B0) PLL REF CLK (MHz)
OFF OFF OFF 19.2
OFF OFF ON 20
OFF ON OFF 24
OFF ON ON 25
ON OFF OFF 26
ON OFF ON 27
ON ON OFF RSVD
ON ON ON RSVD
Table 2-5 Boot Device Selection BOOTMODE [6:3]
SW2.7 (B6) SW2.6 (B5) SW2.5 (B4) SW2.4 (B3) Primary Boot Device Selected
OFF OFF OFF OFF Serial NAND
OFF OFF OFF ON OSPI
OFF OFF ON OFF QSPI
OFF OFF ON ON SPI
OFF ON OFF OFF Ethernet RGMII
OFF ON OFF ON Ethernet RMII
OFF ON ON OFF I2C
OFF ON ON ON UART
ON OFF OFF OFF MMC/ SD card
ON OFF OFF ON eMMC
ON OFF ON OFF USB0
ON OFF ON ON GPMC NAND
ON ON OFF OFF GPMC NOR
ON ON OFF ON Rsvd
ON ON ON OFF xSPI
ON ON ON ON No boot/Dev Boot
Table 2-6 Primary Boot Mode Configuration [9:7]
SW1.2 (B9) SW1.1 (B8) SW2.8 (B7) Primary Boot Mode
RVSD

Read

Mode2

0: RSVD (Read mode is taken from Read

Mode 1)

Read

Mode1

0: OSPI/ 1-1-8 Mode (valid only when

Read Mode 2 is 0)

 Serial NAND
1: SPI/ 1-1-1 Mode (Read mode is taken from Read Mode 2 and Read Mode 1 is ignored)

1: QSPI/ 1-1-4 Mode (valid only when

Read Mode 2 is 0)
RVSD RSVD Csel 0: Boot Flash is on CS 0 OSPI
1: Boot Flash is on CS 1
RVSD RSVD Csel 0: Boot Flash is on CS 0 QSPI
1: Boot Flash is on CS 1
RVSD Mode 0: SPI Mode 0 Csel 0: Boot Flash is on CS 0 SPI
1: SPI Mode 3 1: Boot Flash is on CS 1
0 0 Link stat 0: Phy scan used for speed/duplex setup RGMII1
1: RGMII status register used for speed/ duplex setup
CLKOUT 0: 50MHz clock not generated on CLKOUT0 CLK SRC 0: External clock source 0 RMII1
1: 50MHz clock generated on CLKOUT0 1: Internal clock source
Bus reset 0: Hung bus reset attempt after 1ms RSVD Addr 0: 0x50 I2C0
1: No hung Bus reset attempted 1: 0x51
RSVD RSVD RSVD UART0
1 RSVD Fs/Raw 0: FileSystem Mode MMC/SD Card
1: Raw Mode
RSVD RSVD RSVD eMMC
Core Volt 0: 0.85V Core Voltage Mode 0: DFU(Device) Lane Swap 0: No swapping of DP/DM USB
1: 0.75V Core Voltage 1: MSC(Host) 1: DP/DM is swapped
RSVD RSVD RSVD GPMC NAND
RSVD RSVD RSVD GPMC NOR
RSVD RSVD RSVD RSVD
SFDP 0: SFDP disabled Read Cmd 0: 0x0B Read Command Mode 0: 1S-1S-1S mode at 50MHz xSPI
1: SFDP enabled 1: 0xEE Read Command 1:8D-8D-8D mode at 25MHz
RSVD

ARM/

Thumb

 0: ARM mode No/Dev 0: Development Boot No-boot/Dev boot
1: Thumb mode 1: No Boot
Table 2-7 Backup Boot Mode Selection BOOTMODE [12:10]
SW1.5 (B12) SW1.4 (B11) SW1.3 (B10) Backup Boot Device Selected
OFF OFF OFF None (No backup mode)
OFF OFF ON USB
OFF ON OFF Reserved
OFF ON ON UART
ON OFF OFF Ethernet
ON OFF ON MMC/SD
ON ON OFF SPI
ON ON ON I2C
Table 2-8 Backup Boot Mode Configuration BOOTMODE [13]
SW1.6 (B13) Backup Boot Mode Defaulted Values for Back up Boot Mode
RSVD None
Mode 0: DFU (Device) USB

Core Volt bit = 0

Lane Swap bit = 0
1: MSC (Host)
RSVD RSVD
RSVD UART
Interface 0: RGMII with internal Delay Ethernet Link Stat bit = 0 (If RGMII)
1: RGMII with external clock source ClkOut bit= 0 and Clksrc bit = 1 (If RMII)
1 MMC Mode bit = 0
RSVD SPI

Csel bit = 0

Mode = 0
RSVD I2C

Addr = 0

Bus Rest = 0