An Ethernet network typically includes an MCU, an Ethernet switch and an Ethernet PHY, often with some integration. These components achieve media clock synchronization (Figure 9) through:

• Ethernet MAC.
• Ethernet PHY.
• IEEE802.1AS (gPTP).
• IEEE1722 media clock recovery.
• Media clock generation.

The Ethernet PHY is responsible for transmitting and receiving Ethernet packets. The Ethernet MAC manages data transmission by encapsulating and decapsulating packets. The gPTP protocol synchronizes local clocks across all network devices to maintain a consistent time base. IEEE 1722 media clock recovery uses embedded timing information in Ethernet packets to adjust the audio media clocks: an audio sample clock known as frame synchronization (FSYNC) and an audio data serializer bit clock (SCLK).

Figure 10 shows possible component figurations for an AVB implementation.

TI's solution uses the DP83TG721-Q1 with integrated media clock recovery to resynchronize the local media clock based on the incoming Ethernet stream. The PHY generates the media clock (FSYNC) for audio sample rates and the bit clock (SCLK) in hardware. The PHY hardware also manages the audio packet presentation time handling. The AM263P4-Q1 MCU emulates I²S audio data through its programmable real-time unit to communicate with the TAS6754-Q1 audio amplifier. Figure 11 shows this solution.

Table 3 lists protocols for an Ethernet ring architecture and AVB.