Kit Nguyen

The peak voltage at phase node, V_PH, in a synchronous buck converter is one of the main specifications to determine converter reliability. Designers usually allow phase-node ringing to be as much as 85% to 90% of the MOSFET data sheet’s absolute maximum rating. This margin is necessary for long-term reliability of the converter since the circuit needs to safely operate over a wide range of ambient temperature (-40⁰C to + 85⁰C).

From the driver side, the main factor contributing to phase-node ringing is the gate-driver strength during the turn-on process of the upper MOSFET, FET_UPPER. Let’s analyze its effects in a converter with different gate-driver resistance values.

Figure 1 shows the top level of a synchronous buck converter with the upper MOSFET gate-driver section. The FET_UPPER requires a charge to turn on. This charge comes from the boot capacitor, C_BOOT. The charging path starts from C_BOOT, to R_BOOT, to the pull-up driver P-MOSFET (D_UP), the FET_UPPER input capacitor and back to C_BOOT.

To simplify the comparison, treat R_BOOT as a short and assume MOSFET D_UP behavior as a linear resistance during the turn-on period of the FET_UPPER. A higher D_UP resistance value has a lower peak ringing voltage and lower converter efficiency due to higher switching power losses. A lower resistance value has both a higher peak-ringing voltage and better efficiency.

Figure 2 shows the rising edge of phase-node ringing with different gate-driver strength values. The waveforms are from the TPS543C20 evaluation board with V_IN =12V, V_OUT =1V, F_SW = 500 kHz, I_LOAD = 40A on. The peak ringing voltage of 6Ω D_UP is about 6V higher than 8Ω D_UP. The resistance value of D_UP inside the TPS543C20 can be program via an external communication interface such as an I²C protocol. The waveforms are from the same device and same evaluation board to minimize variation from other components.

Now, let’s compare a 6Ω D_UP along with different boot resistor values to an 8Ω D_UP. From the first order of the circuit analysis, a 6Ω D_UP along with a 2Ω boot resistor should have the same peak ringing voltage as the 8Ω D_UP. Figure 2 also compares the 6Ω D_UP value with 1Ω, 3Ω and 5Ω boot resistors. The peak ringing voltages of these configurations are higher than the 8Ω D_UP value.

You might ask why the 6Ω D_UP with a 2Ω boot resistor and the 8Ω D_UP values do not have the same peak ringing voltage results. This is because the D_UP behaves as a dynamic MOSFET, which requires time during the turn-on process, in comparison to pure resistance as R_BOOT. As a result, the rising slope of a phase node with a 6Ω D_UP and 6Ω D_UP plus boot resistors has the same ratio and is faster than the 8Ω D_UP slope.

Figure 3 compares the efficiency of all configurations. The results clearly correlate our earlier assessment. 6Ω D_UP efficiency is the highest and has the highest peak voltage ringing.  And, 8Ω D_UP efficiency is the lowest with the lowest peak voltage ringing.

It’s critical to optimize the gate-driver strength with the main power-stage MOSFETs to ensure reliability and obtain the highest converter efficiency. A small variation in gate-driver strength can lead to wide variations in converter performance. Consider the TPS543C20 fixed frequency, non-compensation stackable synchronous buck converter for your next design.