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Hey ARM Developers; now you can quickly develop more portable, re-usable and compiler-independent code. MSP432™ microcontroller (MCU) is now fully CMSIS compliant!

The MSP432 MCU software ecosystem will be updated based on the CMSIS-Core. Go to www.ti.com/msp432cmsis to learn how this change impacts you.

MSP432 MCU Software Adopting CMSIS-Core

The Cortex Microcontroller Software Interface Standard (CMSIS) is a common hardware abstraction layer for the Cortex-M processor series and defines generic tool interfaces. The CMSIS enables consistent device support and simple software interfaces to the processor and the peripherals, simplifying software re-use, reducing the learning curve for microcontroller developers and reducing the time to market for new devices. The CMSIS is intended to enable the combination of software components from multiple middleware vendors. There are several components within the CMSIS specifications, out of which many are currently supported by MSP432 microcontroller software and tools infrastructure. Learn more on the CMSIS components go here.

The benefits of the CMSIS-Core and CMSIS in general include:

• Overall CMSIS reduces the learning curve, development costs, and time-to-market. Developers can write software quicker through a variety of easy-to-use standardized software interfaces.
• Consistent software interfaces improve the software portability and re-usability. Generic software libraries and interfaces provide consistent software framework.
• Provides a compiler independent layer that allows using different compilers. CMSIS is supported by all mainstream compilers (ARMCC, IAR and GNU).
• The CMSIS component specific to this MSP432 MCU software update is the CMSIS-Core, which provides the API for the Cortex-M processor core and peripherals. It provides at standardized interface for Cortex-M4F CPU of the MSP432 microcontroller including the SIMD intrinsic functions for Cortex-M4 SIMD instructions. CMSIS-CORE implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals.