This document was translated from a simplified Chinese source. (ZHCTA14)

The DLPC84xx, TI’s latest family of DLP driver controllers, supports a range of DMD variants from .23 1080p to .39/.47 4K. The following sections compare the specifications of the DLPC84xx family with those of the previous-generation DLP 4K driver controller, the DLPC6540.

I. Comparison of Basic Parameters for DLPC84xx and DLPC6540

Similarities:

Both the DLPC84xx chip and the DLPC6540 system have a maximum resolution of 4K @60Hz or 1080p @240Hz. The display signal channel includes the internal test pattern generator (TPG) on the chip, splash image, and external source input. Both chips support a variety of light source types, such as RGB LED, RGB Laser, and LPCW laser color wheel, as well as 3D display modes based on the physical resolution of the DMD.

Differences:

The DLPC6540 only supports the Vx1 input interface, while the DLPC84xx family has FPD-Link and DSI input interfaces in addition to the Vx1 interface (depending on the chip model and software version). The DLPC84xx supports VRR, ultra-low display latency (< 1ms), and a higher color cycle rate. The display latency of the DLPC6540 is approximately the duration of one frame. For example, an input signal at 60Hz features a latency of approximately 16.6ms. The DLPC84xx is capable of driving many more DMD variants, including the .23 1080p, .39 4K, .47 4K, and .47 SST DMDs. These two chips have different DMD interfaces. Specifically, the DLPC6540 supports the High-Speed Serial Interface (HSSI) for the DMD, while the DLPC84xx uses a Sub-LVDS interface for the DMD (the same as the DLPC343x family). The DLPC6540 uses an external parallel NOR Flash, while the DLPC84xx uses an SPI Flash. In addition, the DLPC6540 supports an Auto-lock feature for external sources, whereas the DLPC84xx requires the front-end signal to be configured before being output to the chip.

II. Comparison of Image Processing and Image Quality Specifications

Both the DLPC84xx and DLPC6540 support the overlap mode (turning on two or more non-primary color light sources simultaneously to increase system brightness) with a maximum percentage of 30% for both and up to 20% overlap per single color. Both support image stitching, or manual blending. The DLPC84xx uses a new overlap algorithm, which offers fewer options for adjustment compared to the Brilliant Color used by the DLPC6540. In addition, the DLPC84xx supports up to two-color Y/C/M overlap, while the DLPC6540 supports W (white) overlap in addition to Y/C/M. The DLPC84xx system software includes options for image dither noise, brightness priority, white balance adjustment, and color coordinate calibration, enabling its image quality to reach or closely approach that of the DLPC6540. In addition, the DLPC84xx simplifies the Dynamic Black feature, achieving a result close to the CAIC algorithm used in the DLPC343x system.

III. Comparison of Image Warping Compensation Algorithms

The warping algorithm refers to the adjustment of the geometric coordinates of the input signal pixels, which achieves the purpose of correcting image distortion. For example, when the projected screen or curtain is not a standard plane, when the projection orientation is not perpendicular to the screen, or when optical lens distortion causes the projected image to be distorted, the DLPC chip uses the warping function to set the image coordinate points, thereby correcting the displayed image into a regular rectangle shape, as shown in the figure below.

To reduce image display latency, the DLPC84xx has an optimized internal buffering design, resulting in a slightly smaller number of controllable point grid elements and a narrower adjustment range for the warping function compared to the DLPC6540. The DLPC6540 uses a two-frame image buffering mode. Its advantage is a larger adjustment range for keystone/warping correction, but it introduces longer display latency. The DLPC6540 supports a maximum of 62x32 warping point-grid coordinate adjustments, while the DLPC84xx supports only 32x18. In addition, for four-corner keystone correction, the DLPC6540 can achieve a maximum single-point displacement of 50%, while the DLPC84xx supports a maximum of only 25% for the four-corner keystone adjustment. It is important to note that when simultaneously adjusting the coordinates of the four vertices, consider whether the adjustment ranges are appropriate for both the DLPC84xx and the DLPC6540. In some special cases, the DLPC chip may not be able to implement the set coordinates; the algorithm may choose the closest achievable position. Warping correction may degrade image quality or cause display artifacts within certain unsupported adjustment ranges.

Summary

Compared to the previous-generation DLP 4K driver chip, the DLPC84xx offers a smaller package size and lower power consumption, further reducing system BOM costs. It also supports display latency of less than 1ms and variable refresh rate (VRR). Based on a low-latency design architecture, the DLPC84xx family is not a simple upgrade of the DLPC6540, but a new design platform compatible with a wider range of DMD variants, capable of driving the majority of DMDs using a Sub-LVDS interface. When designing a DLP system, we should consider the weights of various parameters and metrics and choose the appropriate DLPC chip.