SWRA574B October   2017  – February 2020 AWR1243 , AWR2243

 

  1.   AWR2243 Cascade
    1.     Trademarks
    2. 1 Cascaded AWR2243 System
    3. 2 Synchronization of AWR2243 Chips
      1. 2.1 20 GHz (FMCW) RF LO Sync
      2. 2.2 Digital Frame Sync
        1. 2.2.1 Frame (Burst) and Chirp Timing in AWR2243
        2. 2.2.2 Frame (Burst) and Chirp Timing in a Cascaded System
        3. 2.2.3 Inter Chip Imbalance of Digital Sync Timing
      3. 2.3 40 MHz (System) Reference Clock Synchronization
    4. 3 Connectivity
      1. 3.1 20 GHz LO Sync Pins Connectivity
      2. 3.2 DIG_SYNC Connectivity
      3. 3.3 40 MHz (System) Reference Clock Connectivity
    5. 4 20 GHz LO Sync Link Budget
    6. 5 Software Messaging
      1. 5.1 Configuration of Devices
      2. 5.2 Configuration of Frames
        1. 5.2.1 Similar Configuration Across AWR2243 Devices
        2. 5.2.2 Dissimilar Configuration Across AWR2243 Devices
      3. 5.3 Triggering of Frames
      4. 5.4 Example Usage
      5. 5.5 Other Usages
    7. 6 Advantages of AWR2243 Cascading System
    8. 7 References
  2.   Revision History

5.3 Triggering of Frames

The frames can be triggered using the frame trigger message, AWR_FRAME_TRIG_MSG.

The frame configuration message, briefly introduced in an earlier section, allows configuring frames to be triggered directly using the frame trigger message (SWTRIGGER mode) or through high pulses on the hardware pin, called SYNC_IN or DIG_SYNC, subsequent to the reception of the frame trigger message (HWTRIGGER mode). The SWTRIGGER mode has an associated triggering uncertainty of several tens of microseconds (the frame repetition rate has no uncertainty). The HWTRIGGER mode has much lower triggering uncertainty, detailed in a subsequent section.

In cascaded chip systems, typically, the MULTICHIP_SLAVE devices are configured in HWTRIGGER mode and get triggered by the MULTICHIP_MASTER device. The MULTICHIP_MASTER device is typically triggered in SWTRIGGER mode.

Typically, the host processor needs to issue the frame trigger message to the slave devices to get them ready to receive the DIG_SYNC_IN from the master device. After receiving the acknowledgment, the host processor can issue the frame trigger message to the master device. This starts off a series of frames (as many as programmed in the frame configuration message) and for each such frame, the master device generates a high pulse on its DIG_SYNC_OUT pin, which, through the DIG_SYNC_IN pins, causes all the chips to start the chirp timing, transmission and reception synchronously.