SWRZ095A January   2020  – June 2022 CC2642R-Q1

PRODUCTION DATA  

  1.   Abstract
  2.   Trademarks
  3. 1Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support-Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Advisories
    1.     Power_03
    2.     PKA_01
    3.     PKA_02
    4.     I2C_01
    5.     I2S_01
    6.     CPU_01
    7.     CPU_02
    8.     CPU_03
    9.     CPU_Sys_01
    10.     Sys_01
    11.     Sys_03
    12.     SYSCTRL_01
    13.     SRAM_01
    14.     GPTM_01
    15.     ADC_01
    16.     ADC_02
    17.     ADC_03
    18.     ADC_04
    19.     ADC_05
  6. 4Revision History

I2S_01

I2S Bus Faults are Not Reported

Revisions Affected:

Revision F and earlier

Details:

The I2S module will not set the bus error interrupt flag (I2S0.IRQFLAGS.BUS_ERR) if an I2S read or write causes a system bus fault that results from access to illegal addresses (usage error).

Workaround:

Software must ensure that memory area used by the I2S DMA is accessible, meaning that the memory is powered on and the system bus is connected..

As an example; The TI-provided SPI driver SPICC26X2DMA.c will ensure that the flash memory is kept accessible also in Idle power mode if the transmit buffer address starts with 0x0 to ensure no bus faults occur. A similar approach needs to be taken if writing a peripheral driver utilizing I2S.